Method of forming dynamic random access memory circuitry using SOI and isolation trenches

Claim 2

A semiconductor processing method of forming dynamic random access memory circuitry comprising the following steps: providing an electrically conductive capacitor cell plate substrate; providing an electrically insulative layer over the cell plate; providing a layer of semiconductive material on the electrically insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; patterning and etching the SOI layer to define active area region islands and isolation trenches between the islands; filling the isolation trenches with electrically insulative material; providing capacitor openings through the SOI layer and electrically insulative layer into the capacitor cell plate substrate; providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; providing respective capacitor storage nodes over the capacitor dielectric layer within the capacitor openings, the respective storage nodes being in ohmic electrical connection with the SOI layer; after providing the capacitor storage nodes, filling any remaining portions of the capacitor container openings with electrically insulative material; providing a gate dielectric layer atop the SOI layer islands; providing electrically conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; providing opposing FET source and drain regions within the SOI layer; and providing bit lines outwardly of the word lines, the bit lines electrically connecting with selected drain regions.

Claim 3

The semiconductor processing method of claim 1 further comprising providing a protective capping layer over the SOI layer before defining the active area region islands and isolation trenches, and removing the protective capping layer from the SOI layer islands prior to providing the gate dielectric layer atop the SOI layer islands.

Claim 4

The semiconductor processing method of claim 1 further comprising providing an etch stop layer over the SOI layer, the steps of filling the isolation trenches and remaining portions of the capacitor contact openings comprising depositing respective layers of insulating material and subsequently etching such layers in a common step using the etch stop layer as an etch stop to such etching.

Claim 5

The semiconductor processing method of claim 3 wherein the common step etching is conducted by chemical-mechanical polishing.

Claim 6

The semiconductor processing method of claim 1 further comprising providing a protective capping layer over the SOI layer before defining the active area region islands and isolation trenches, and removing the protective capping layer from the SOI layer islands prior to providing the gate dielectric layer atop the SOI layer islands; and further comprising providing an etch stop layer over the protective capping layer, the steps of filling the isolation trenches and remaining portions of the capacitor contact openings comprising depositing respective layers of insulating material and subsequently etching such layers in a common step using the etch stop layer as an etch stop to such etching.

Claim 7

The semiconductor processing method of claim 1 wherein the islands and trenches are formed before providing the capacitor openings.

Claim 8

The semiconductor processing method of claim 1 wherein the isolation trenches are filled by depositing an insulating layer, the step of providing the capacitor openings sequentially comprising: depositing and patterning photoresist over the insulating layer to define a pattern for such capacitor openings; with the photoresist in place, etching through the insulating layer and the SOI layer stopping on the capacitor cell plate substrate; stripping the photoresist from outwardly of the insulating layer; and etching into the cell plate substrate using the insulating layer as a hard mask for such cell plate etching.

Claim 9

The semiconductor processing method of claim 1 wherein the electrically insulative layer has an outer surface and an inner surface, the step of providing the capacitor storage nodes comprises providing a first conductive layer to within the respective capacitor openings, the first conductive layer having an outer surface which is positioned between the outer and inner surfaces of the electrically insulative layer; and providing a second conductive layer within the respective capacitor openings in ohmic electrical connection with the first conductive layer and with the SOI layer.

Claim 10

The semiconductor processing method of claim 1 wherein the SOI layer has an outer surface, the respective capacitor storage nodes have an outer surface which is positioned below the SOI layer outer surface.

Claim 11

The semiconductor processing method of claim 1 wherein the electrically insulative layer has an outer surface and an inner surface, the step of providing the capacitor storage nodes comprises providing a first conductive layer to within the respective capacitor openings, the first conductive layer having an outer surface which is positioned between the outer and inner surfaces of the electrically insulative layer; and providing a second conductive layer within the respective capacitor openings in ohmic electrical connection with the first conductive layer and with the SOI layer; and wherein the SOI layer has an outer surface, the second conductive layer having an outer surface which is positioned below the SOI layer outer surface.

Claim 12

The semiconductor processing method of claim 1 wherein the capacitor cell plate substrate comprises a bulk substrate region of a semiconductor material wafer.

Claim 13

A dynamic random access memory circuit array produced according to the process of claim 1.

Claim 14

A dynamic random access memory circuit array produced according to the process of claim 11.

Claim 15

A semiconductor processing method of forming dynamic random access memory circuitry comprising the following steps: providing an electrically conductive capacitor cell plate substrate; providing an electrically insulative layer over the cell plate; providing a layer of semiconductive material on the electrically insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; providing a protective capping layer over the SOI layer; providing an etch stop layer over the SOI layer; patterning and etching the SOI layer, etch stop layer and capping layer to define active area region islands and isolation trenches between the islands; filling the isolation trenches with electrically insulative material; after forming the active area region islands and isolation trenches between the islands, providing capacitor openings through the SOI layer and electrically insulative layer into the capacitor cell plate substrate; providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; providing respective capacitor storage nodes over the capacitor dielectric layer within the capacitor openings, the respective storage nodes being in ohmic electrical connection with the SOI layer; after providing the capacitor storage nodes, filling any remaining portions of the capacitor container openings with electrically insulative material; the steps of filling the isolation trenches and remaining portions of the capacitor contact openings comprising depositing respective layers of insulating material and subsequently etching such layers in a common step using the etch stop layer as an etch stop to such etching; removing the protective capping layer from the SOI layer islands; after removing the protective capping layer, providing a gate dielectric layer atop the SOI layer islands; providing electrically conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; providing opposing FET source and drain regions within the SOI layer; and providing bit lines outwardly of the word lines, the bit lines electrically connecting with selected drain regions.

Claim 16

A semiconductor processing method of forming dynamic random access memory circuitry comprising the following steps: providing an electrically conductive capacitor cell plate substrate; providing an electrically insulative layer over the cell plate; providing a layer of semiconductive material on the electrically insulative layer thereby defining a semiconductor-on-insulator (SOI) layer; providing a protective capping layer over the SOI layer; providing an etch stop layer over the SOI layer; patterning and etching the SOI layer, etch stop layer and capping layer to define active area region islands and isolation trenches between the islands; filling the isolation trenches with electrically insulative material; after forming the active area region islands and isolation trenches between the islands, providing capacitor openings through the SOI layer and electrically insulative layer into the capacitor cell plate substrate; providing a capacitor dielectric layer over the cell plate substrate within the capacitor openings; providing respective capacitor storage nodes over the capacitor dielectric layer within the capacitor openings, the respective storage nodes being in ohmic electrical connection with the SOI layer; after providing the capacitor storage nodes, filling any remaining portions of the capacitor container openings with electrically insulative material; the steps of filling the isolation trenches and remaining portions of the capacitor contact openings comprising depositing respective layers of insulating material and subsequently etching such layers in a common step using the etch stop layer as an etch stop to such etching; removing the protective capping layer from the SOI layer islands; after removing the protective capping layer, providing a gate dielectric layer atop the SOI layer islands; providing electrically conductive word lines over the gate dielectric layer on the islands and over the filled isolation trenches; providing opposing FET source and drain regions within the SOI layer; and providing bit lines outwardly of the word lines, the bit lines electrically connecting with selected drain regions.

Claim 17

The semiconductor processing method of claim 14 wherein the common step etching is conducted by chemical-mechanical polishing.

Claim 18

The semiconductor processing method of claim 14 wherein the step of providing the capacitor openings sequentially comprises: depositing and patterning photoresist over the insulating layer filling the isolation trenches to define a pattern for such capacitor openings; with the photoresist in place, etching through the insulating layer filling the isolation trenches and the SOI layer stopping on the capacitor cell plate substrate; stripping the photoresist from outwardly of the insulating layer filling the isolation trenches; and etching into the cell plate substrate using the insulating layer filling the isolation trenches as a hard mask for such cell plate etching.

Claim 19

The semiconductor processing method of claim 14 wherein the electrically insulative layer has an outer surface and an inner surface, the step of providing the capacitor storage nodes comprises providing a first conductive layer to within the respective capacitor openings, the first conductive layer having an outer surface which is positioned between the outer and inner surfaces of the electrically insulative layer; and providing a second conductive layer within the respective capacitor openings in ohmic electrical connection with the first conductive layer and with the SOI layer.

Claim 20

The semiconductor processing method of claim 14 wherein the SOI layer has an outer surface, the respective capacitor storage nodes have an outer surface which is positioned below the SOI layer outer surface.

Claim 21

The semiconductor processing method of claim 14 wherein the electrically insulative layer has an outer surface and an inner surface, the step of providing the capacitor storage nodes comprises providing a first conductive layer to within the respective capacitor openings, the first conductive layer having an outer surface which is positioned between the outer and inner surfaces of the electrically insulative layer; and providing a second conductive layer within the respective capacitor openings in ohmic electrical connection with the first conductive layer and with the SOI layer; and wherein the SOI layer has an outer surface, the second conductive layer having an outer surface which is positioned below the SOI layer outer surface.

Claim 22

The semiconductor processing method of claim 14 wherein the step of providing the capacitor openings sequentially comprises: depositing and patterning photoresist over the insulating layer filling the isolation trenches to define a pattern for such capacitor openings; with the photoresist in place, etching through the insulating layer filling the isolation trenches and the SOI layer stopping on the capacitor cell plate substrate; stripping the photoresist from outwardly of the insulating layer filling the isolation trenches; and etching into the cell plate substrate using the insulating layer filling the isolation trenches as a hard mask for such cell plate etching; and wherein the electrically insulative layer has an outer surface and an inner surface, the step of providing the capacitor storage nodes comprises providing a first conductive layer to within the respective capacitor openings, the first conductive layer having an outer surface which is positioned between the outer and inner surfaces of the electrically insulative layer; and providing a second conductive layer within the respective capacitor openings in ohmic electrical connection with the first conductive layer and with the SOI layer.

Claim 23

The semiconductor processing method of claim 14 wherein the step of providing the capacitor openings sequentially comprises: depositing and patterning photoresist over the insulating layer filling the isolation trenches to define a pattern for such capacitor openings; with the photoresist in place, etching through the insulating layer filling the isolation trenches and the SOI layer stopping on the capacitor cell plate substrate; stripping the photoresist from outwardly of the insulating layer filling the isolation trenches; and etching into the cell plate substrate using the insulating layer filling the isolation trenches as a hard mask for such cell plate etching; and wherein the SOI layer has an outer surface, the respective capacitor storage nodes have an outer surface which is positioned below the SOI layer outer surface.

Claim 24

The semiconductor processing method of claim 14 wherein the step of providing the capacitor openings sequentially comprises: depositing and patterning photoresist over the insulating layer filling the isolation trenches to define a pattern for such capacitor openings; with the photoresist in place, etching through the insulating layer filling the isolation trenches and the SOI layer stopping on the capacitor cell plate substrate; stripping the photoresist from outwardly of the insulating layer filling the isolation trenches; and etching into the cell plate substrate using the insulating layer filling the isolation trenches as a hard mask for such cell plate etching; wherein the SOI layer has an outer surface, the respective capacitor storage nodes have an outer surface which is positioned below the SOI layer outer surface; and wherein the electrically insulative layer has an outer surface and an inner surface, the step of providing the capacitor storage nodes comprises providing a first conductive layer to within the respective capacitor openings, the first conductive layer having an outer surface which is positioned between the outer and inner surfaces of the electrically insulative layer; and providing a second conductive layer within the respective capacitor openings in ohmic electrical connection with the first conductive layer and with the SOI layer.

Claim 25

The semiconductor processing method of claim 14 wherein the step of providing the capacitor openings sequentially comprises: depositing and patterning photoresist over the insulating layer filling the isolation trenches to define a pattern for such capacitor openings; with the photoresist in place, etching through the insulating layer filling the isolation trenches and the SOI layer stopping on the capacitor cell plate substrate; stripping the photoresist from outwardly of the insulating layer filling the isolation trenches; and etching into the cell plate substrate using the insulating layer filling the isolation trenches as a hard mask for such cell plate etching; and wherein the electrically insulative layer has an outer surface and an inner surface, the step of providing the capacitor storage nodes comprises providing a first conductive layer to within the respective capacitor openings, the first conductive layer having an outer surface which is positioned between the outer and inner surfaces of the electrically insulative layer; and providing a second conductive layer within the respective capacitor openings in ohmic electrical connection with the first conductive layer and with the SOI layer; and wherein the SOI layer has an outer surface, the second conductive layer having an outer surface which is positioned below the SOI layer outer surface.

Claim 26

The semiconductor processing method of claim 14 wherein the capacitor cell plate substrate comprises a bulk substrate region of a semiconductor material wafer.

Claim 27

A dynamic random access memory circuit array produced according to the process of claim 14.

Claim 28

A dynamic random access memory circuit array produced according to the process of claim 24.