Deflection distortion correcting circuit

Claim 2

A deflection distortion correcting circuit comprising: counting means for counting basic clock pulses in synchronism with a vertical synchronizing signal and outputting a count value; first-difference calculating means for sequentially calculating a first-difference value based on said count value and a first reference value, said first-difference calculating means determining a period of a basic parabolic wave; second-difference calculating means for sequentially calculating a second difference value based on said count value and a second reference value, said second-difference calculating means determining a period of a correcting-use parabolic wave; means for integrating said first difference value and outputting a first integrated value; means for integrating said second difference value and outputting a second integrated value; integrated-value adding means for calculating a sum of said first integrated value and said second integrated value; means for generating a pulse width modulation signal based on said sum; and means for integrating said pulse width modulation signal and outputting a signal for correcting a deflection distortion.

Claim 3

A deflection distortion correcting circuit comprising: counting means for counting basic clock pulses in synchronism with a vertical synchronizing signal and outputting a count value; first-difference calculating means for sequentially calculating a first difference value based on count value and a first reference value, said first-difference calculating means determining a period of a basic parabolic wave; second-difference calculating means for sequentially calculating a second difference value based on a second reference value and said count value, said second-difference calculating means determining a period of a correcting-use parabolic wave; difference adding means for calculating a sum of said first difference value and said second difference value; difference-sum integrating means for integrating said sum; means for generating a pulse width modulation signal based on said integrated sum; and means for integrating said pulse width modulation signal and outputting a signal for correcting deflection distortion.

Claim 4

A deflection distortion correcting circuit comprising: counting means for counting basic clock pulses in synchronism with a vertical synchronizing signal and outputting a count value; first-difference calculating means for sequentially calculating a first difference value based on count value and a first reference value, said first-difference calculating means determining a period of a basic parabolic wave; second-difference calculating means for sequentially calculating a second difference value based on a second reference value and said count value, said second-difference calculating means determining a period of a correcting-use parabolic wave; difference adding means for calculating a sum of said first difference value and said second difference value; difference-sum integrating means for integrating said sum; means for generating a pulse width modulation signal based on said integrated sum; and means for integrating said pulse width modulation signal and outputting a signal for correcting deflection distortion.

Claim 5

The deflection distortion correcting circuit according to claim 1, further comprising: first multiplying means for multiplying said count value by a first amplitude gain, and outputting a first multiplied value; and second multiplying means for multiplying said first reference value by said first amplitude gain and outputting a second multiplied value; third multiplying means for multiplying said count value by a second amplitude gain and outputting a third multiplied value; and fourth multiplying means for multiplying said second reference value by said second amplitude gain and outputting a fourth multiplied value, wherein said first-difference calculating means calculates said first-difference value based on said first and second multiplied values, and said second-difference calculating means calculates said second-difference value based on said third and fourth multiplied values.

Claim 6

The deflection distortion correcting circuit according to claim 2, wherein said first difference calculating means includes first multiplying means for multiplying said count value by a first amplitude gain and outputting a first multiplied value, and second multiplying means for multiplying said first reference value by said first amplitude gain and outputting a second multiplied value, wherein said first-difference calculating means calculates said first difference value based on said first multiplied value and said second multiplied value, and said second difference calculating means includes third multiplying means for multiplying said count value by a second amplitude gain and outputting a third multiplied value, and fourth multiplying means for multiplying said second reference value by said second amplitude gain and outputting a fourth multiplied value, wherein said second-difference calculating means calculates said second difference value based on said third multiplied value and said fourth multiplied value.

Claim 7

A deflection distortion correcting circuit comprising: counting means for counting basic clock pulses in synchronism with a vertical synchronizing signal and outputting a count value; means for time-division multiplexing a first amplitude gain and a second amplitude gain; means for time division multiplexing a first reference value and a second reference value; first multiplying means for multiplying said count value by said first and second time-division multiplexed amplitude gains, said first multiplying means outputting a first multiplied value; second multiplying means for multiplying said time-division multiplexed first and second reference values by said first and second time-division multiplexed amplitude gains, said second multiplying means outputting a second multiplied value; difference calculating means for calculating a difference value based on said first multiplied value and said second multiplied value; means for separating said calculated difference value into at least first and second values; means for adding said at least first and second values to produce an added value; means for integrating said added value to produce an integrated value; means for generating said pulse width modulation signal based on said integrated value; and means for integrating said pulse width modulation signal and outputting a signal for correcting deflection distortion.

Claim 8

A deflection distortion correcting circuit comprising: counting means for counting basic clock pulses in synchronism with a vertical synchronizing signal and outputting a count value; means for time-division multiplexing a first amplitude gain and a second amplitude gain; means for time division multiplexing a first reference value and a second reference value; first multiplying means for multiplying said count value by said first and second time-division multiplexed amplitude gains, said first multiplying means outputting a first multiplied value; second multiplying means for multiplying said time-division multiplexed first and second reference values by said first and second time-division multiplexed amplitude gains, said second multiplying means outputting a second multiplied value; difference calculating means for calculating a difference value based on said first multiplied value and said second multiplied value; means for separating said calculated difference value into at least first and second values; means for adding said at least first and second values to produce an added value; means for integrating said added value to produce an integrated value; means for generating said pulse width modulation signal based on said integrated value; and means for integrating said pulse width modulation signal and outputting a signal for correcting deflection distortion.

Claim 9

The deflection distortion correcting circuit according to claim 1, wherein said counting means previously counts said basic clock pulses over a single vertical scanning period, and said first and second reference values are calculated in accordance with said previously counted basic clock pulses.

Claim 10

The deflection distortion correcting circuit according to claim 2, wherein said counting means previously counts said basic clock pulses over a single vertical scanning period, and said first and second reference values are calculated in accordance with said previously counted basic clock pulses.

Claim 11

The deflection distortion correcting circuit according to claim 3, wherein said counting means previously counts said basic clock pulses over a vertical scanning period, and said first and second reference values are calculated in accordance with said previously counted basic clock pulses.

Claim 12

The deflection distortion correcting circuit according to claim 4, wherein said counting means previously counts said basic clock pulses over a vertical scanning period, and said first and second reference values are calculated in accordance with said previously counted basic clock pulses.

Claim 13

The deflection distortion correcting circuit according to claim 5, wherein said counting means previously counts said basic clock pulses over a vertical scanning period, and said first and second reference values are calculated in accordance with said previously counted basic clock pulses.

Claim 14

The deflection distortion correcting circuit according to claim 1, wherein said counting means previously counts said basic clock pulses over a vertical scanning period for each of a plurality of vertical scanning periods, and said first and second reference values are calculated in accordance with each of said previously counted basic clock pulses.

Claim 15

The deflection distortion correcting circuit according to claim 2, wherein said counting means previously counts said basic clock pulses over a single vertical scanning period for each of a plurality of vertical scanning periods, and said first and second reference values are calculated in accordance with each of said previously counted basic clock pulses.

Claim 16

The deflection distortion correcting circuit according to claim 3, wherein said counting means previously counts said basic clock pulses over a single vertical scanning period for each of a plurality of vertical scanning periods, and said first and second reference values are calculated in accordance with each of said previously counted basic clock pulses.

Claim 17

The deflection distortion correcting circuit according to claim 4, wherein said counting means previously counts said basic clock pulses over a single vertical scanning period for each of a plurality of vertical scanning periods, and said first and second reference values are calculated in accordance with each of said previously counted basic clock pulses.

Claim 18

The deflection distortion correcting circuit according to claim 5, wherein said counting means previously counts said basic clock pulses over a single vertical scanning period for each of a plurality of vertical scanning periods, and said first and second reference values are calculated in accordance with each of said previously counted basic clock pulses.

Claim 19

The deflection distortion correcting circuit according to claim 2, wherein said difference adding means includes means for specifying a timing at which said second difference value is to be added to said first difference value.

Claim 20

The deflection distortion correcting circuit according to claim 1, further comprising: means for compressing or amplifying said sum obtained from said integrated-value adding means.

Claim 21

The deflection distortion correcting circuit according to claim 2, further comprising: means for compressing or amplifying said sum obtained from said difference adding means.

Claim 22

A deflection distortion correcting circuit of claim 1, wherein said vertical synchronizing signal is separated from an image signal.

Claim 23

A deflection distortion correcting circuit of claim 2, wherein said vertical synchronizing signal is separated from an image signal.

Claim 24

A deflection distortion correcting circuit of claim 5, wherein said vertical synchronizing signal is separated from an image signal.

Claim 27

The method of claim 22, wherein said step (b) comprises calculating a difference between said counted number and said first reference value to obtain said first value.

Claim 28

The method of claim 22, wherein said step (c) comprises calculating a difference between said counted number and said second reference value to obtain said second value.

Claim 29

The method of claim 22, wherein said step (f) comprises adding said integrated first and second values to obtain said third value.

Claim 30

The method of claim 22, further comprising: (i) adding said integrated first and second values when said integrated second value is equal to or greater than zero.

Claim 31

The method of claim 22, further comprising: (i) compressing said first reference value to obtain said second reference value.

Claim 32

The method of claim 22, wherein said step (b) includes (b1) multiplying said counted number and a first amplitude gain to obtain a first multiplied value, (b2) multiplying said first reference value and said first amplitude gain to obtain a second multiplied value, and (b3) calculating a difference between said first and second multiplied values to obtain said first value, and said step (c) includes (c1) multiplying said counted value and a second amplitude gain to obtain a third multiplied value, (c2) multiplying said second reference value and said second amplitude gain to obtain a fourth multiplied value, and (c3) calculating a difference between said third and fourth multiplied values to obtain said second value.

Claim 35

The method of claim 29, wherein said step (b) comprises calculating a difference between said counted number and said first reference value to obtain said first value.

Claim 36

The method of claim 29, wherein said step (c) comprises calculating a difference between said counted number and said second reference value to obtain said second value.

Claim 37

The method of claim 29, wherein said step (d) comprises adding Said first and second values to obtain said third value.

Claim 38

The method of claim 29, further comprising: (h) adding said first and second values when said second value is equal to or greater than zero.

Claim 39

The method of claim 29, further comprising: (i) compressing said first reference value to obtain said second reference value.

Claim 42

The method of claim 35, wherein said step (g) includes (g1) inputting said third value to a first flip-flop triggered by said switching signal to obtain a fifth value, (g2) inputting said third value to a second flip-flop triggered by an inverted switching signal to obtain a sixth value, and (g3) adding said fifth and sixth values to obtain a modified third value.

Claim 43

The method of claim 36, further comprising: (j) adding said sixth value to said fifth value when said fifth value is equal to or greater than zero.

Claim 44

The method of claim 35, wherein said step (f) includes calculating a difference between said first and second values to obtain said third value.