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EP0503915A2
Expired / Lapsed
EP
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Correction signal generating circuit for television receiver
Assignee: Sony Corp
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Filing: 1992-03-11
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Granted: —
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Expires: 2012-03-11
Abstract
Abstract A correction signal generating circuit for a television receiver includes a counter for counting a pulse synchronised with a horizontal sync. signal, a memory for storing a correction datum and coefficient, an unit for multiplying and adding contents of the counter and memory, a signal feedback loop for supplying an output from the multiplying and adding unit to an input thereof, and a control unit for controlling operation of the memory and the multiplying and adding unit, thereby generating a correction signal.
Inventors
- 👤 Shinichirou Miyazaki
- 👤 Kyoichi Murakami
- 👤 Takahiko Tamura
- 👤 Hiroshi Murayama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 19:38
CPC Classifications
H; H04; H04N; H04N3/00; H04N3/10; H04N3/16; H04N3/22; H04N3/23; H04N3/233; H04N3/2335
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
83 words
A correction signal generating circuit for a television receiver, comprising: counter means for counting pulse synchronized with a horizontal sync. signal; memory means for storing a correction datum and coefficient; means for multiplying and adding contents of said counter means and said memory means; a signal feedback loop for supplying an output from said means for multiplying and adding to an input of said means for multiplying and adding; and control means for controlling operation of said means to generate a correction signal.
Claim 2
Dependent Claim
21 words
A correction signal generating circuit according to claim 1, wherein the correction signal is supplied to a pincushion distortion correcting circuit.
Claim 3
Dependent Claim
28 words
A correction signal generating circuit according to claim 1, wherein the correction signal is a parabolic waveform signal having a period of that of a vertical sync. signal.
Claim 4
Dependent Claim
18 words
A correction signal generating circuit according to claim 1, wherein said signal feedback loop is a bus line.
Claim 5
Dependent Claim
21 words
A correction signal generating circuit according to claim 1, wherein the coefficient is determined in accordance with a vertical sync. frequency.
Claim 6
Dependent Claim
116 words
A correction signal generating circuit comprising: a single multiplier, a single adder, a memory for storing data and a coefficient, and a controller for controlling the operations of the multiplier, adder and memory, wherein a calculation utilizing the multiplier and the adder on the basis of a count value of a horizontal sync. signal per one field and contents of the memory is performed repeatedly for plural times to obtain desired deflection distortion correcting signals of high orders such as a saw tooth waveform signal represented by [Y SAW = (CX³ = DX² + X) B + A] and a parabolic waveform signal represented by [Y PARA = (GX⁴ + X² + HX) FB² + E].
References Cited (Backward Citations)
No citation records indexed.
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