Apparatus for suspending the bus cycle of a microprocessor by inserting wait states

Claim 2

A data processing device comprising: a control part for processing data and communicating with one of a plurality of peripheral devices during a bus cycle; a plurality of registers, each register being connected to said control part for storing data which designates a length of a wait period; and a plurality of wait circuits, each wait circuit suspending said bus cycle in response to a wait request signal and maintaining the bus cycle suspension regardless of a succeeding wait signal by outputting a wait instruction signal, "OR" logic means, having said wait instruction signals of each wait circuit as inputs and having an output to said control part; wherein said data processing device holds a signal to be applied to one of the plurality of peripheral devices accessed during said wait period, and resumes said bus cycle after a lapse of said wait period.

Claim 3

The microprocessor according to claim 1 wherein said control part, said wait circuit, and said register are provided in an Large Scale Integrated chip.

Claim 4

A data processing device comprising: a control part for processing data and communicating with one of a plurality of peripheral devices during a bus cycle and for outputting chip select signals; a plurality of registers, each register being connected to said control part for storing data which designates a length of a wait period; a plurality of wait circuits, each wait circuit suspending the bus cycle in response to a wait request signal and maintaining the bus cycle suspension regardless of a succeeding wait signal by outputting a wait instruction signal; and a plurality of address selectors, for detecting each chip-select signal outputted from the control part in correspondence with said plurality of the peripheral devices as wait request signals and for outputting the results to a corresponding wait circuit; "OR" logic means, having said wait instruction signals of each wait circuit as inputs and having an output to said control part; wherein said data processing device holds a signal to be applied to one of said plurality of peripheral devices during said wait period, and resumes said bus cycle after a lapse of said wait period.

Claim 5

A data processing device comprising: a control part for processing data and communicating with one of a plurality of peripheral devices during a bus cycle and for outputting chip select signals; a plurality of registers, each register being connected to said control part for storing data which designates a length of a wait period; a plurality of wait circuits, each wait circuit suspending the bus cycle in response to a wait request signal and maintaining the bus cycle suspension regardless of a succeeding wait signal by outputting a wait instruction signal; and a plurality of address selectors, for detecting each chip-select signal outputted from the control part in correspondence with said plurality of the peripheral devices as wait request signals and for outputting the results to a corresponding wait circuit; "OR" logic means, having said wait instruction signals of each wait circuit as inputs and having an output to said control part; wherein said data processing device holds a signal to be applied to one of said plurality of peripheral devices during said wait period, and resumes said bus cycle after a lapse of said wait period.

Claim 6

The data processing device according to claim 3 wherein said data processing device prioritizes a wait request from a peripheral device having a largest number of wait states provided in the register when a plurality of the peripheral devices simultaneously generate wait requests to the control part.

Claim 7

A microcomputer comprising: a microprocessor for processing operations in a predetermined bus cycle; and an address selector for detecting a chip-select signal outputted from a control part to peripheral devices as a wait request signal provided outside and connected to said microprocessor; wherein said peripheral devices connected to and accessible by the microprocessor include a control part for processing operations and generating access control signals to its peripheral devices; state number setting means connected to said control part for storing data which designates a length of a wait period; a plurality of wait circuits connected to said state number setting means generating a wait instruction signal in response to a wait request signal; means for causing the bus cycles in said control part to wait for a period corresponding to the state number provided by said state number setting means including "OR" logic means, having the wait instruction signals from each of said plurality of wait circuits as inputs and having an output to said control part; and means for holding a signal to be applied to one of a plurality of peripheral devices accessed during said wait period and resuming said bus cycle after a lapse of said wait period.

Claim 8

A microcomputer comprising: a microprocessor for processing operations in a predetermined bus cycle; and an address selector for detecting a chip-select signal outputted from a control part to peripheral devices as a wait request signal provided outside and connected to said microprocessor; wherein said peripheral devices connected to and accessible by the microprocessor include a control part for processing operations and generating access control signals to its peripheral devices; state number setting means connected to said control part for storing data which designates a length of a wait period; a plurality of wait circuits connected to said state number setting means generating a wait instruction signal in response to a wait request signal; means for causing the bus cycles in said control part to wait for a period corresponding to the state number provided by said state number setting means including "OR" logic means, having the wait instruction signals from each of said plurality of wait circuits as inputs and having an output to said control part; and means for holding a signal to be applied to one of a plurality of peripheral devices accessed during said wait period and resuming said bus cycle after a lapse of said wait period.

Claim 9

A microcomputer comprising: a microprocessor for processing operations in a predetermined bus cycle including: a control part for processing operations and generating access control signals to peripheral devices; state number setting means connected to said control part for storing data which designates a length of a wait period; a plurality of wait circuits connected to said state number setting means, generating a wait instruction signal in response to a wait request signal; a plurality of address selectors for detecting each access control signal outputted from the control part corresponding to one of said plurality of the peripheral devices as a wait request signal and for outputting results to a corresponding wait circuit; means for causing the bus cycle in said control part to wait for a period corresponding to a state number provided by said state number setting means including "OR" logic means, having the wait instruction signals from each of said plurality of wait circuits as inputs and having an output to said control part; means for holding a signal to be applied to one of a plurality of peripheral devices accessed during said wait period and resuming said bus cycle after a lapse of said wait period.

Claim 10

A microcomputer comprising: a microprocessor for processing operations in a predetermined bus cycle including: a control part for processing operations and generating access control signals to peripheral devices; state number setting means connected to said control part for storing data which designates a length of a wait period; a plurality of wait circuits connected to said state number setting means, generating a wait instruction signal in response to a wait request signal; a plurality of address selectors for detecting each access control signal outputted from the control part corresponding to one of said plurality of the peripheral devices as a wait request signal and for outputting results to a corresponding wait circuit; means for causing the bus cycle in said control part to wait for a period corresponding to a state number provided by said state number setting means including "OR" logic means, having the wait instruction signals from each of said plurality of wait circuits as inputs and having an output to said control part; means for holding a signal to be applied to one of a plurality of peripheral devices accessed during said wait period and resuming said bus cycle after a lapse of said wait period.