Timing circuit and method for controlling the operation of cyclical devices

Claim 3

The method according to claim 1 wherein said control data signals from a binary word having at least one bit for each of said devices, one state of each bit signifying that the corresponding device is to be actuated and the other state of the same bit signifying that the corresponding device is not to be actuated.

Claim 4

The method according to claim 2 wherein each of said ready signals forms a binary bit, one state of said binary bit signifying that the corresponding device has completed a cycle of operation and is ready to commence a subsequent cycle of operation.

Claim 5

The method according to claim 3 wherein each control data bit is compared with the corresponding ready signal bit to determine whether or not the ready signal bit is in said state signifying completion of a cycle of operation when the corresponding control data bit is in the state signifying that the corresponding device is to be actuated.

Claim 6

The method according to claim 4 wherein each control data bit which is in the state signifying that the corresponding device is to be actuated is maintained in that state at least until the last ready signal bit for the selected devices switches to the state signifying that the corresponding device has completed a cycle of operation and is ready to commence a subsequent cycle of operation.

Claim 7

The method according to claim 1 wherein one of said devices is a first digital memory in which a plurality of binary instruction words is stored at addresses which are arranged in a predetermined program sequence and said memory including a read-out circuit and means operable to advance said read-out circuit from one step of said program sequence to the next on successive read-outs of instruction words from said memory.

Claim 8

The method according to claim 6 wherein one of said devices is a second digital memory in which a plurality of binary data words are stored at corresponding addresses, said second digital memory including a read-out circuit, and said instruction words including portions which specify the address of a data word which is to be read-out for use in the corresponding program step.

Claim 9

The method according to claim 7 wherein one of said devices is a third digital memory in which a plurality of binary control words are stored at corresponding addresses, said third memory including a read-out circuit, said instruction words including portions which specify the address of a control word which is to be read-out for use in the corresponding program step, and each control word signifying predetermined digital operations which are to be performed in pursuance of the corresponding instruction word.

Claim 10

The method according to claim 7 wherein binary words are simultaneously read-out of said first and second memories on at least one of said program steps.

Claim 11

The method according to claim 8 wherein binary words are simultaneously read-out of said first, second and third memories on at least one of said program steps.

Claim 12

The method according to claim 1 wherein said further control data signals are generated in coincidence with the trailing edge of said strobe.

Claim 13

A timing circuit for operating any number of a plurality of devices each of which is operable when actuated to execute a cycle of operation, said timing circuit comprising: control logic means for generating control data signals specifying which devices are selected to be actuated at a given time; actuation circuit means coupled between said control logic circuit means and said devices for actuating the selected devices; a plurality of ready signal circuit means each associated with a corresponding device for generating a ready signal after the corresponding device has completed a cycle of operation and is ready to commence a subsequent cycle of operation; comparison circuit means coupled to said ready signal circuit means and control logic means for comparing said ready signals to said control data signals to determine when the last ready signal for the actuated devices has been generated; and strobe generation circuit means coupled to said comparison circuit means for generating a strobe after said last ready signal for the actuated devices has been generated to signify that all of the selected devices have completed a single cycle of operation, said strobe generation circuit means including means for generating the leading edge of said strobe in response to said last ready signal, and means for generating the trailing edge of said strobe in response to the resetting of all of said ready signals.

Claim 14

A timing circuit for operating any number of a plurality of devices each of which is operable when actuated to execute a cycle of operation, said timing circuit comprising: control logic means for generating control data signals specifying which devices are selected to be actuated at a given time; actuation circuit means coupled between said control logic circuit means and said devices for actuating the selected devices; a plurality of ready signal circuit means each associated with a corresponding device for generating a ready signal after the corresponding device has completed a cycle of operation and is ready to commence a subsequent cycle of operation; comparison circuit means coupled to said ready signal circuit means and control logic means for comparing said ready signals to said control data signals to determine when the last ready signal for the actuated devices has been generated; and strobe generation circuit means coupled to said comparison circuit means for generating a strobe after said last ready signal for the actuated devices has been generated to signify that all of the selected devices have completed a single cycle of operation, said strobe generation circuit means including means for generating the leading edge of said strobe in response to said last ready signal, and means for generating the trailing edge of said strobe in response to the resetting of all of said ready signals.

Claim 15

The timing circuit according to claim 12 wherein said control logic circuit means generates control data signals which form a binary control word having at least one bit for each of said devices, one state of each bit signifying that the corresponding device is to be actuated and the other state signifying that the corresponding device is not to be actuated.

Claim 16

The timing circuit according to claim 13 wherein said actuation circuit means comprises: select means associated with each device for actuating the device in response to a binary input signal; and means for gating the corresponding bit of said control word to the select input of each device to actuate the device when specified by said control word bit.

Claim 17

The timing circuit according to claim 14 wherein said actuation circuit means comprises: a control register coupled to said control logic circuit means for receiving and storing said control word; a plurality of AND gates each having two inputs and an output, one AND gate for each of said devices, one input of each AND gate being coupled to a corresponding stage of said control register to receive a corresponding bit of said control word, the output of each AND gate being coupled to the select input of the corresponding digital device, the other input of each AND gate being coupled to a common conductor; and start circuit means coupled to said common conductor for enabling said AND gates at predetermined times to gate said control word to the select input of said devices to actuate the selected devices.

Claim 18

The timing circuit according to claim 14 wherein each ready signal circuit means generates a binary ready signal, one state of said binary ready signal signifying that the corresponding device has completed a cycle of operation and is ready to commence a subsequent cycle of operation, and wherein said comparison circuit means comprises: a plurality of NAND gates each having two inputs and an output, one NAND gate for each of said devices, one input of each NAND gate being coupled to the corresponding bit of said control word and the other input of each NAND gate being coupled to the corresponding ready signal, and the output of all of said NAND gates being coupled to said strobe generator circuit means.

Claim 19

The timing circuit according to claim 16 wherein said strobe generator circuit means comprises: an AND gate having N+1 inputs where N is the number of devices and having an output, N of said AND gate inputs being coupled respectively to the outputs of said NAND gates; an additional NAND gate having N inputs and an output, each input of said additional NAND gate being coupled to a corresponding one of said ready signals, and the output of said additional NAND gate being coupled to the remaining input of said AND gate; and the output of said AND gate comprising the output of said strobe generator circuit means.

Claim 20

The timing circuit according to claim 15 wherein said start circuit means comprises a NOR gate having two inputs and an output, the output of said NOR gate being coupled to said common conductor, one input of said NOR gate being coupled to the output of said strobe generator circuit means, and the other input of said NOR gate serving as a START input for the timing circuit.

Claim 21

The timing circuit according to claim 18 wherein said control register has a LOAD input and wherein the output of said NOR gate is coupled to said LOAD input.