Semi-asynchronous clock system

Claim 1

A CLOCK CIRCUIT CONTROL TO CONNECT A SYSTEM CLOCK CIRCUIT TO THE CENTRAL PROCESSING UNIT OF A DATA PROCESSING SYSTEM HAVING: A CENTRAL PROCESSING UNIT TO CONVERT INPUT DATA, TO TEMPORARILY RETAIN THE RESULTS OF CONVERSION, AND TO PARTIALLY CONVERT A SECOND SET OF DATA WHILE THE SAID RESULTS ARE RETAINED, A CHECKING UNIT TO DETERMINE PRIOR TO UTILIZATION OF SAID RESULT, THAT SAID RESULT IS COMPATIBLE WITH THE INPUT DATA FOR SAID RESULT AND A SYSTEM CLOCK CIRCUIT TO CONTROL SAID PROCESSING SYSTEM; SAID CLOCK CIRCUIT CONTROL COMPRISING: A FIRST BISTABLE DEVICE TO NORMALLY ENABLE SAID CLOCK CIRCUIT TO CONTROL SAID CENTRAL PROCESSING UNIT, A SIGNAL CIRCUIT CONTROLLED BY SAID CENTRAL PROCESSING UNIT TO ENABLE SAID CLOCK CIRCUIT TO CHANGE THE STATE OF SAID FIRST BISTABLE DEVICE TO THEREBY BLOCK CLOCK CIRCUIT CONTROL OF SAID UNIT WHEREBY A DATA PROCESSING OPERATION MAY BE HALTED, A PLURALITY OF SECOND BISTABLE DEVICES, EACH SETTABLE WHEN SAID CHECKING UNIT HAS HAD SUFFICIENT TIME TO COMPLETE A CORRESPONDING TEST ON SAID RESULT AND AN ENABLING CIRCUIT CONTROLLED BY SAID PLURALITY OF SECOND BISTABLE DEVICES TO RE-ENABLE SAID CLOCK CIRCUIT CONTROL OVER SAID CENTRAL PROCESSING UNIT.