US5581734A
Expired / Lapsed
US
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Multiprocessor system with shared cache and data input/output circuitry for transferring data amount greater than system bus capacity
Assignee: International Business Machines Corp
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Filing: 1993-08-02
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Granted: 1996-12-03
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Expires: 2013-08-02
Abstract
Abstract A high performance shared cache is provided to support multiprocessor systems and allow maximum parallelism in accessing the cache by the processors, servicing one processor request in each machine cycle, reducing system response time and increasing system throughput. The shared cache of the present invention uses the additional performance optimization techniques of pipelining cache operations (loads and stores) and burst-mode data accesses. By including built-in pipeline stages, the cache is enabled to service one request every machine cycle from any processing element. This contributes to reduction in the system response time as well as the throughput. With regard to the burst-mode data accesses, the widest possible data out of the cache can be stored to, and retrieved from, the cache by one cache access operation. One portion of the data is held in logic in the cache (on the chip), while another portion (corresponding to the system bus width) gets transferred to the requesting element (processor or memory) in one cycle. The held portion of the data can then be transferred in the following machine cycle.
Inventors
- 👤 Michael T. DiBrino
- 👤 Dwain A. Hicks
- 👤 George M. Lattimore
- 👤 Kimming K. So
- 👤 Hanaa Youssef
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 19:58
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0877; G06F12/0879; G06F12/0806; G06F12/084; G06F12/0844; G06F12/0846; G06F12/0851; G06F12/0855; G06F12/10; G06F12/1027; G06F12/1045
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
119 words
A data processing system, having a plurality of processing units, comprising: a cache for storing data to be utilized by said processing units; a system bus for transferring data between said cache and said processing units; and circuit means for transferring, in a single operation, input data to said cache from said processing units and output data from said cache to said processing units, in an amount greater than a capacity of said system bus, said circuit means sequentially storing said input data as data words, combining adjacent ones of said data words and providing said combined data word to said cache; wherein said single operation simultaneously transfers said data between said cache and said plurality of processing units.
Claim 2
Dependent Claim
119 words
A data processing system, having a plurality of processing units, comprising: a cache for storing data to be utilized by said processing units; a system bus for transferring data between said cache and said processing units; and circuit means for transferring, in a single operation, input data to said cache from said processing units and output data from said cache to said processing units, in an amount greater than a capacity of said system bus, said circuit means sequentially storing said input data as data words, combining adjacent ones of said data words and providing said combined data word to said cache; wherein said single operation simultaneously transfers said data between said cache and said plurality of processing units.
Claim 3
Dependent Claim
23 words
The system according to claim 1 further comprising pipeline means for latching data which is being stored into and retrieved from said cache.
Claim 4
Dependent Claim
19 words
The system according to claim 1 wherein said cache comprises plural interleaved sections each with input and output ports.
Claim 5
Dependent Claim
34 words
The system according to claim 1 wherein said output means comprises: means for separating said combined data word into plural data words; and means for placing said plural data words on said system bus.
Claim 6
Dependent Claim
23 words
The system according to claim 4 wherein said means for combining comprises a multiplexer, and said means for storing comprises a store queue.
Claim 7
Dependent Claim
28 words
The system according to claim 5 wherein said means for separating comprises a multiplexer and a latch, and said means for placing comprises a register and a driver.
Claim 8
Independent Claim
58 words
The system according to claims 6, further comprising arbitration means for awarding access to one of a plurality of interleaved sections in said cache to the processing unit having the least recent access to said one of said interleaved sections, when more than one of said processing units are concurrently requesting access to the one said interleaved section.
Claim 9
Dependent Claim
20 words
The system according to claim 1, further comprising means for directly transferring data between plural ones of said processing units.
Claim 10
Dependent Claim
37 words
The system according to claim 8 wherein said means for directly transferring data comprises means for providing said data directly from said means for inputting to said means for outputting, such that the data bypasses said cache.
Claim 11
Independent Claim
124 words
A method of storing data in data processing system, having a plurality of processing units, said method comprising the steps of: storing data to be utilized by said processing units in a cache; providing data between said cache and said processing units on a system bus; and transferring, in a single operation, input data to said cache from said processing units and output data from said cache to said processing units, in an amount greater than a capacity of said system bus, by sequentially storing said input data as data words, combining adjacent ones of said data words and providing said combined data word to said cache; wherein said single operation simultaneously transfers said data between said cache and said plurality of processing units.
Claim 12
Independent Claim
124 words
A method of storing data in data processing system, having a plurality of processing units, said method comprising the steps of: storing data to be utilized by said processing units in a cache; providing data between said cache and said processing units on a system bus; and transferring, in a single operation, input data to said cache from said processing units and output data from said cache to said processing units, in an amount greater than a capacity of said system bus, by sequentially storing said input data as data words, combining adjacent ones of said data words and providing said combined data word to said cache; wherein said single operation simultaneously transfers said data between said cache and said plurality of processing units.
Claim 13
Dependent Claim
23 words
The method according to claim 10 further comprising a step of latching data which is being stored into and retrieved from said cache.
Claim 14
Dependent Claim
35 words
The method according to claim 11 wherein said step of storing comprises a step of simultaneously accessing said cache by said plurality of processing units through plural interleaved sections, each with input and output ports.
Claim 15
Dependent Claim
33 words
The method according to claim 10 wherein said step of outputting comprises steps of: separating said combined data word into plural data words; and placing said plural data words on said system bus.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-03 | 2000-06-03 | 2000-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-03 | 2004-06-03 | 2004-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-03 | 2008-06-03 | 2008-12-03 | $7700.00 | Window Closed / Lapsed |