Patent US5580797A successfully refreshed from Google Patents.
US5580797A
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US
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Method of making SOI Transistor
Assignee: Sony Corp
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Filing: 1994-05-18
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Granted: 1996-12-03
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Expires: 2014-05-18
Abstract
Abstract A lateral bipolar transistor capable of forming a narrow-sized diffusion region, such as a base width, is disclosed. The transistor exhibits no scattering in the direction of the depth of the width of the diffusion region. Emitter resistance is reduced by varying an impurity diffusion source at substantially a uniform concentration in a semiconductor portion and forming a diffusion region by diffusion from the impurity diffusion source. The bipolar transistor has an SOI structure. A method of making such device is also disclosed.
Inventors
- 👤 Hiroyuki Miwa
- 👤 Takayuki Gomi
- 👤 Katsuyuki Kato
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:27
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/311; H10D10/01; H10D10/041
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
144 words
A method of manufacturing a semiconductor device which comprises: a step of providing an insulating substrate and a semiconductor portion; a step of forming on said substrate a laminate structure comprising a first conductor and a first insulator, a step of forming a first side wall comprising a second conductor in contact with a side portion of said laminate structure, a step of forming a second side wall comprising a second insulator in contact with said first side wall, a step of removing at least one of a portion of said insulating substrate and said semiconductor portion using the side portion of said laminate structure and said second insulator as a mask, a step of burying a third conductor into a recess formed by said step of removing, and a step of forming a diffusion region using the third conductor as a diffusion source.
Claim 2
Independent Claim
144 words
A method of manufacturing a semiconductor device which comprises: a step of providing an insulating substrate and a semiconductor portion; a step of forming on said substrate a laminate structure comprising a first conductor and a first insulator, a step of forming a first side wall comprising a second conductor in contact with a side portion of said laminate structure, a step of forming a second side wall comprising a second insulator in contact with said first side wall, a step of removing at least one of a portion of said insulating substrate and said semiconductor portion using the side portion of said laminate structure and said second insulator as a mask, a step of burying a third conductor into a recess formed by said step of removing, and a step of forming a diffusion region using the third conductor as a diffusion source.
Claim 3
Dependent Claim
31 words
A method of manufacturing a semiconductor device as defined in claim 1, wherein the first and the second conductors comprise poly Si or a laminate structure of poly Si and metal.
Claim 4
Dependent Claim
21 words
A method of manufacturing a semiconductor device as defined in claim 1 or 2, wherein the third conductor comprises poly Si.
Claim 5
Independent Claim
100 words
A method of manufacturing a semiconductor device which comprises: a step of removing a portion of a semiconductor portion situated in an insulating portion, a step of burying a conductor to the portion removed from the semiconductor portion, a step of forming a diffusion region using said conductor as a diffusion source, a step of removing a portion of said insulating portion using the conductor as a mask, thereby exposing at least a portion of said conductor buried in said portion to be removed from the semiconductor portion, and a step of selectively siliciding said exposed portion of said conductor.
Claim 6
Independent Claim
100 words
A method of manufacturing a semiconductor device which comprises: a step of removing a portion of a semiconductor portion situated in an insulating portion, a step of burying a conductor to the portion removed from the semiconductor portion, a step of forming a diffusion region using said conductor as a diffusion source, a step of removing a portion of said insulating portion using the conductor as a mask, thereby exposing at least a portion of said conductor buried in said portion to be removed from the semiconductor portion, and a step of selectively siliciding said exposed portion of said conductor.
Claim 7
Dependent Claim
20 words
A method of manufacturing a semiconductor device as defined in claim 4, wherein the semiconductor portion comprises an SOI structure.
Claim 8
Dependent Claim
51 words
A method of manufacturing a semiconductor device as defined in claim 4 or 5, wherein the semiconductor device is a bipolar transistor and the step of forming the diffusion region using the conductor as a diffusion source is a step of forming at least one of an emitter and a base.
Claim 9
Dependent Claim
23 words
A method of manufacturing a semiconductor device as defined in any one of claim 4 or 5, wherein the conductor comprises poly Si.
Claim 10
Independent Claim
183 words
A method of manufacturing a semiconductor device which comprises: a step of forming a laminate structure comprising a first conductor and a first insulator over a substrate in which a semiconductor portion is formed in an insulating portion, a step of forming a first side wall comprising a second conductor in contact with a side portion of said laminate structure, a step of forming a second side wall comprising a second insulator in contact with said first side wall, a step of removing a portion of said semiconductor portion using the side portion of said laminate structure and said second side wall as a mask, a step of burying a third conductor into the removed portion of the semiconductor portion, a step of forming a diffusion region using said third conductor as a diffusion source, a step of removing a portion of said insulating portion using said third conductor as a mask thereby providing an exposed portion of the third conductor buried in said removed portion of the semiconductor portion, and a step of selectively siliciding the exposed portion of said third conductor.
Claim 11
Independent Claim
183 words
A method of manufacturing a semiconductor device which comprises: a step of forming a laminate structure comprising a first conductor and a first insulator over a substrate in which a semiconductor portion is formed in an insulating portion, a step of forming a first side wall comprising a second conductor in contact with a side portion of said laminate structure, a step of forming a second side wall comprising a second insulator in contact with said first side wall, a step of removing a portion of said semiconductor portion using the side portion of said laminate structure and said second side wall as a mask, a step of burying a third conductor into the removed portion of the semiconductor portion, a step of forming a diffusion region using said third conductor as a diffusion source, a step of removing a portion of said insulating portion using said third conductor as a mask thereby providing an exposed portion of the third conductor buried in said removed portion of the semiconductor portion, and a step of selectively siliciding the exposed portion of said third conductor.
Claim 12
Dependent Claim
20 words
A method of manufacturing a semiconductor device as defined in claim 8, wherein the semiconductor portion has an SOI structure.
Claim 13
Dependent Claim
52 words
A method of manufacturing a semiconductor device as defined in claim 8 or 9, wherein the semiconductor device is a bipolar transistor and a step of forming the diffusion region using said third conductor as a diffusion source is a step of forming at least one of an emitter and a base.
Claim 14
Dependent Claim
39 words
A method of manufacturing a semiconductor device as defined in any one of claim 8 or 9, wherein at least one of said first and second conductors comprises poly Si or a laminate structure of poly Si and metal.
Claim 15
Dependent Claim
23 words
A method of manufacturing a semiconductor device as defined in any of claim 8 or 9, wherein the third conductor comprises poly Si.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-12-03 | 2000-06-03 | 2000-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-12-03 | 2004-06-03 | 2004-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-12-03 | 2008-06-03 | 2008-12-03 | $7700.00 | Window Closed / Lapsed |