Patent US5578874A successfully refreshed from Google Patents.
US5578874A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Hermetically self-sealing flip chip
Assignee: Raytheon Co
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Filing: 1994-06-14
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Granted: 1996-11-26
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Expires: 2014-06-14
Abstract
Abstract A package containing an integrated circuit has all of its I/O contacts on one of the package faces. The periphery of that face is processed to be wettable with solder. The substrate to which the package is to be attached has corresponding contacts and has a solder wettable ring comparable to the ring at the periphery at the package face. When the package is positioned on the substrate it is hermetically sealed therearound by soldering the two rings together, such as by reflow soldering.
Inventors
- 👤 Garrett I. Kurogi
- 👤 Matthew J. Swass
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 03:38
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/30; H05K3/32; H05K3/34; H05K3/341; H05K3/3431; H05K3/3436; H10; H10W; H10W76/00; H10W76/60; H05K1/00; H05K1/02; H05K1/0213; H05K1/0216; H05K1/0218; H05K2201/00; H05K2201/09; H05K2201/09209; H05K2201/09654; H05K2201/09781; H05K2203/00; H05K2203/11; H05K2203/1147; H10W72/00; H10W72/071; H10W72/072; H10W72/07231; H10W72/07236; H10W72/07251; H10W72/20; Y; Y02; Y02P; Y02P70/00; Y02P70/50; Y10; Y10T; Y10T29/00; Y10T29/49; Y10T29/49002; Y10T29/49117; Y10T29/49124; Y10T29/49126; Y10T29/4913; Y10T29/49144
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
316 words
A hermetically sealed flip chip structure comprising: a dielectric substrate (12) having a face and having solder-coated contacts (28, 30, 32) mounted on said face thereof and with at least one of said contacts (28, 30) having corresponding vias (34, 36) through said substrate (12) for connection to said at least one of said contacts (28, 30); a barrier (40) surrounding said surface contacts (28, 30, 32) on said substrate (12) said barrier (40) having a contact (42) thereon; an integrated circuit-containing body (14), a face on said body (14), integrated circuit contacts (16, 18, 20) on said face of said body (14), said integrated circuit contacts (16, 18, 20) on said face of said body (14) corresponding in position to said contacts (28, 30, 32) on said substrate, a barrier (24) on said face of said body (14), said barrier (24) surrounding said contacts (16, 18, 20) on said face of said body (14), said barrier (24) having a contact (26) thereon, said barrier (24) on said body (14) corresponding to said barrier (40) on said substrate (12) so that when said contacts (16, 18, 20) on said body (14) are against said contacts (28, 30, 32) on said substrate (12), said barriers (24, 40) lie against each other, said barriers (24, 40) being sealed together so as to hermetically seal said contacts (16, 18, 20; 28, 30, 32,) between said body (14) and said substrate (12), and said contact (42) on said barrier (40) corresponding to said contact (26) on said barrier (24), wherein there is at least one printed wiring strip (38) on the surface of said dielectric substrate (12) and there is an insulator layer (44) over said printed wiring strip (38), said surrounding barrier (40) on said substrate (12) being positioned over said insulating layer (44) so that said surrounding barrier (40) is electrically isolated from said printed wiring strip (38).
Claim 2
Dependent Claim
316 words
A hermetically sealed flip chip structure comprising: a dielectric substrate (12) having a face and having solder-coated contacts (28, 30, 32) mounted on said face thereof and with at least one of said contacts (28, 30) having corresponding vias (34, 36) through said substrate (12) for connection to said at least one of said contacts (28, 30); a barrier (40) surrounding said surface contacts (28, 30, 32) on said substrate (12) said barrier (40) having a contact (42) thereon; an integrated circuit-containing body (14), a face on said body (14), integrated circuit contacts (16, 18, 20) on said face of said body (14), said integrated circuit contacts (16, 18, 20) on said face of said body (14) corresponding in position to said contacts (28, 30, 32) on said substrate, a barrier (24) on said face of said body (14), said barrier (24) surrounding said contacts (16, 18, 20) on said face of said body (14), said barrier (24) having a contact (26) thereon, said barrier (24) on said body (14) corresponding to said barrier (40) on said substrate (12) so that when said contacts (16, 18, 20) on said body (14) are against said contacts (28, 30, 32) on said substrate (12), said barriers (24, 40) lie against each other, said barriers (24, 40) being sealed together so as to hermetically seal said contacts (16, 18, 20; 28, 30, 32,) between said body (14) and said substrate (12), and said contact (42) on said barrier (40) corresponding to said contact (26) on said barrier (24), wherein there is at least one printed wiring strip (38) on the surface of said dielectric substrate (12) and there is an insulator layer (44) over said printed wiring strip (38), said surrounding barrier (40) on said substrate (12) being positioned over said insulating layer (44) so that said surrounding barrier (40) is electrically isolated from said printed wiring strip (38).
Claim 3
Dependent Claim
33 words
The flip chip structure of claim 1 wherein said barrier on said body is formed as a metallic layer on said face of said body and a solder bump on said metallic layer.
Claim 4
Dependent Claim
33 words
The chip structure of claim 2 wherein said barrier on said substrate comprises a metallic barrier on said face of said substrate and a solder bump on said metallic barrier on said substrate.
Claim 5
Dependent Claim
21 words
The chip structure of claim 3 wherein said solder bumps are fused together to provide said hermetic seal surrounding said contacts.
Claim 6
Dependent Claim
30 words
The chip structure of claim 4 wherein said surrounding barrier is at the periphery of said body so that a visible fillet is positioned between said body and said substrate.
Claim 7
Dependent Claim
57 words
The chip structure of claim 5 wherein there is at least one printed wiring strip on the surface of said substrate and there is an insulator layer over said printed wiring strip, said surrounding barrier on said substrate being positioned over said insulating layer so that said surrounding barrier is electrically isolated from said printed wiring strip.
Claim 8
Dependent Claim
33 words
The chip structure of claim 1 wherein said barrier on said substrate comprises a metallic barrier on said face of said substrate and a solder bump on said metallic barrier on said substrate.
Claim 9
Dependent Claim
57 words
The chip structure of claim 7 wherein there is at least one printed wiring strip on the surface of said substrate and there is an insulator layer over said printed wiring strip, said surrounding barrier on said substrate being positioned over said insulating layer so that said surrounding barrier is electrically isolated from said printed wiring strip.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-26 | 2008-05-27 | 2008-11-26 | $7700.00 | Window Closed / Lapsed |