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US5578848A
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Ultra thin dielectric for electronic devices and method of making same
Assignee: Intellectual Ventures Holding 40 LLC
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Filing: 1995-09-18
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Granted: 1996-11-26
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Expires: 2015-09-18
Abstract
Abstract High quality, ultra thin SiO 2 /Si 3 N 4 (ON) dielectric layers have been fabricated by in situ multiprocessing and low pressure rapid-thermal N 2 O-reoxidation (LRTNO) of Si 3 N 4 films. Si 3 N 4 film was deposited on the RTN-treated polysilicon by rapid-thermal chemical vapor deposition (RT-CVD) using SiH 4 and NH 3 , followed by in situ low pressure rapid-thermal reoxidation in N 2 O (LRTNO) or in O 2 (LRTO) ambient. Results show that ultra thin (T ox ,eq =˜29 Å) ON stacked film capacitors with LRTNO have excellent electrical properties, and reliability.
Inventors
- 👤 Dim-Lee Kwong
- 👤 Giwan Yoon
- 👤 Jonghan Kim
- 👤 Liang-Kai Han
- 👤 Jiang Yan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:19
CPC Classifications
H; H10; H10P; H10P14/00; H10P14/60; H10P14/65; H10P14/6516; H10P14/6518; H10P14/6519; H10P14/6522; H10D; H10D1/00; H10D1/01; H10D1/045; H10D1/047; H10D1/60; H10D1/68; H10D64/00; H10D64/01; H10D64/013; H10D64/01302; H10D64/01332; H10D64/01336; H10D64/0134; H10D64/01344; H10D64/60; H10D64/66; H10D64/68; H10D64/693; H10P14/63; H10P14/6302; H10P14/6316; H10P14/6322; H10P14/6529; H10P14/66; H10P14/662; H10P14/69; H10P14/692; H10P14/6921; H10P14/69215; H10P14/6326; H10P14/6328; H10P14/6334; H10P14/668; H10P14/6681; H10P14/6682; H10P14/6922; H10P14/6927; H10P14/694; H10P14/6943; H10P14/69433; Y; Y10; Y10S; Y10S438/00; Y10S438/954
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
149 words
In a dynamic random access memory, a capacitor structure comprising a first doped silicon electrode, a first layer of thermally grown Si 3 N 4 on a surface of said first electrode, a second layer of vapor deposited Si 3 N 4 on said first layer, a third layer of thermally grown oxynitride (ON) on said second layer, and a second electrode on said layer of ON, and a field effect transistor including a source region, a drain region, and a channel region between said source region and said drain region, a gate electrode over said channel region, and a dielectric between said gate electrode and said channel region, said dielectric comprising a fourth layer of thermally grown Si 3 N 4 , a fifth layer of vapor deposited Si 3 N 4 on said fourth layer, and a sixth layer of thermally grown ON on said fifth layer.
Claim 2
Dependent Claim
149 words
In a dynamic random access memory, a capacitor structure comprising a first doped silicon electrode, a first layer of thermally grown Si 3 N 4 on a surface of said first electrode, a second layer of vapor deposited Si 3 N 4 on said first layer, a third layer of thermally grown oxynitride (ON) on said second layer, and a second electrode on said layer of ON, and a field effect transistor including a source region, a drain region, and a channel region between said source region and said drain region, a gate electrode over said channel region, and a dielectric between said gate electrode and said channel region, said dielectric comprising a fourth layer of thermally grown Si 3 N 4 , a fifth layer of vapor deposited Si 3 N 4 on said fourth layer, and a sixth layer of thermally grown ON on said fifth layer.
Claim 3
Dependent Claim
84 words
A field effect transistor comprising a semiconductor body having a source region, a drain region, and a channel region between said source region and said drain region, a gate electrode over said channel region, and a dielectric between said gate electrode and said channel region, said dielectric comprising a first layer of thermally grown Si 3 N 4 , a second layer of vapor deposited Si 3 N 4 on said first layer, and a layer of thermally grown ON on said second layer.
Claim 4
Dependent Claim
84 words
A field effect transistor comprising a semiconductor body having a source region, a drain region, and a channel region between said source region and said drain region, a gate electrode over said channel region, and a dielectric between said gate electrode and said channel region, said dielectric comprising a first layer of thermally grown Si 3 N 4 , a second layer of vapor deposited Si 3 N 4 on said first layer, and a layer of thermally grown ON on said second layer.
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-11-26 | 2000-05-27 | 2000-11-26 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-26 | 2004-05-27 | 2004-11-26 | $3760.00 | Window Closed / Lapsed |
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