US5577223A — Dynamic random access memory (DRAM) with cache an…

Claim 1

Independent Claim 108 words

A dynamic RAM comprising: (a) an array of memory cells including a sub-array having a memory cell located at a cross point of a word line and a bit line; (b) an X decoder for decoding an X address of the sub-array and for selecting the word line; (c) a column sense amplifier for detecting and amplifying data on the bit line read out from the memory cell; (d) a sub-array control circuit for controlling the column sense amplifier as a cache; and (e) a TAG block corresponding to the sub-array for storing a TAG address only for the sub-array and for receiving and storing the X address.

Claim 2

Dependent Claim 108 words

A dynamic RAM comprising: (a) an array of memory cells including a sub-array having a memory cell located at a cross point of a word line and a bit line; (b) an X decoder for decoding an X address of the sub-array and for selecting the word line; (c) a column sense amplifier for detecting and amplifying data on the bit line read out from the memory cell; (d) a sub-array control circuit for controlling the column sense amplifier as a cache; and (e) a TAG block corresponding to the sub-array for storing a TAG address only for the sub-array and for receiving and storing the X address.

Claim 3

Dependent Claim 36 words

A dynamic RAM as set forth in claim 1, wherein the TAG block includes a control circuit for purging the TAG block and the column sense amplifier after completion of a refresh operation on the sub-array.

Claim 4

Dependent Claim 81 words

A dynamic RAM as set forth in claim 2, wherein the array of memory cells includes a plurality of memory cell sub-arrays, the RAM further comprising a plurality of TAG blocks respectively corresponding to the sub-arrays, wherein the control circuit further activates the plurality of sub-arrays and the corresponding plurality of TAG blocks concurrently during an access operation and a refresh operation, and wherein the X address is provided by the X decoder to control the activated sub-arrays and TAG blocks.

Claim 5

Dependent Claim 67 words

A dynamic RAM as set forth in claim 2, wherein the array of memory cells includes a plurality of memory cell sub-arrays, the RAM further comprising a plurality of TAG blocks respectively corresponding to the sub-arrays, wherein the control circuit further activates the plurality of sub-arrays and the corresponding plurality of TAG blocks with each separate cycle during an access operation, and concurrently during a refresh operation.

Claim 6

Dependent Claim 39 words

A dynamic RAM as set forth in claim 1, wherein the X decoder is located adjacent to and parallel with the TAG block in a central region of a chip and the sub-array is located outside the central region.

Claim 7

Dependent Claim 123 words

A dynamic RAM as set forth in claim 1, wherein the TAG block further comprises: (a) a TAG address holding circuit for storing lower bits of the X address in response to a TAG Icad signal; (b) an address comparison circuit for comparing the TAG address with the lower bits of the X address and for issuing a comparison signal indicating a result of the comparison; and (c) a block control circuit for generating a TAG determination signal, including a TAG flag for storing a TAG address state and for accepting the comparison signal from the address comparison circuit; a sub-array address indicating upper bits of the X address; a refresh signal for refreshing the sense amplifier; and first and second timing signals.

Claim 8

Dependent Claim 174 words

A dynamic RAM comprising: (a) a plurality of sub-arrays, each sub-array including a plurality of memory cells, each of the memory cells being connected to a corresponding cross point between a word line and a bit line; (b) an X decoder for decoding an X address corresponding to one of the memory cells and for selecting the word line corresponding to the memory cell corresponding to the X address; (c) a column sense amplifier for detecting and amplifying data on the bit line read out from one of the memory cells; (d) a plurality of TAG blocks, each of the TAG blocks connected to a corresponding one of the sub-arrays, for storing a TAG address corresponding to the sub-array and for receiving the decoded X address; (e) a plurality of sub-array control circuits for controlling the column sense amplifier as a cache; and (f) a sense amplifier mediation circuit for validating one of the sub-array control circuits and for invalidating another of the sub-array control circuits to regulate control of the column sense amplifier.

Claim 9

Dependent Claim 174 words

A dynamic RAM comprising: (a) a plurality of sub-arrays, each sub-array including a plurality of memory cells, each of the memory cells being connected to a corresponding cross point between a word line and a bit line; (b) an X decoder for decoding an X address corresponding to one of the memory cells and for selecting the word line corresponding to the memory cell corresponding to the X address; (c) a column sense amplifier for detecting and amplifying data on the bit line read out from one of the memory cells; (d) a plurality of TAG blocks, each of the TAG blocks connected to a corresponding one of the sub-arrays, for storing a TAG address corresponding to the sub-array and for receiving the decoded X address; (e) a plurality of sub-array control circuits for controlling the column sense amplifier as a cache; and (f) a sense amplifier mediation circuit for validating one of the sub-array control circuits and for invalidating another of the sub-array control circuits to regulate control of the column sense amplifier.

Claim 10

Dependent Claim 43 words

A dynamic RAM as set forth in claim 7, wherein each of the TAG blocks includes a control circuit for purging the TAG block and the column sense amplifier after completion of a refresh operation on the sub-array corresponding to the TAG block.

Claim 11

Dependent Claim 43 words

A dynamic RAM as set forth in claim 7, wherein the X decoder is located adjacent to and parallel with the plurality of TAG blocks in a central region of a chip and the plurality of sub-arrays is located outside the central region.

Claim 12

Dependent Claim 141 words

A dynamic RAM including a plurality of sub-arrays having a plurality of memory cells, the dynamic RAM comprising; (a) a decoding circuit for decoding an address to provide an intermediate address; (b) a TAG memory including a plurality of TAG blocks, each of the TAG blocks corresponding to one of the plurality of sub-arrays; and (c) a first intermediate address bus for passing the intermediate address between the decoding circuit and the TAG memory; each of the TAG blocks including: (i) a TAG address holding circuit for storing the intermediate address and for providing the intermediate address to the decoding circuit; (ii) an address comparison circuit for comparing an address on the intermediate address bus with a stored address in the TAG address holding circuit; and (iii) a purge circuit for deactivating all bits held by the TAG address holding circuit.

Claim 13

Dependent Claim 141 words

A dynamic RAM including a plurality of sub-arrays having a plurality of memory cells, the dynamic RAM comprising; (a) a decoding circuit for decoding an address to provide an intermediate address; (b) a TAG memory including a plurality of TAG blocks, each of the TAG blocks corresponding to one of the plurality of sub-arrays; and (c) a first intermediate address bus for passing the intermediate address between the decoding circuit and the TAG memory; each of the TAG blocks including: (i) a TAG address holding circuit for storing the intermediate address and for providing the intermediate address to the decoding circuit; (ii) an address comparison circuit for comparing an address on the intermediate address bus with a stored address in the TAG address holding circuit; and (iii) a purge circuit for deactivating all bits held by the TAG address holding circuit.

Claim 14

Dependent Claim 42 words

A dynamic RAM as set forth in claim 10, further including an X decoder located adjacent to and parallel with the TAG memory in a central region of a chip and wherein the plurality of sub-arrays is located outside the central region.

Claim 15

Dependent Claim 74 words

A dynamic RAM as set forth in claim 10, further comprising a column sense amplifier for detecting and amplifying data read out from one of the memory cells; a plurality of sub-array control circuits for controlling the column sense amplifier as a cache; and a sense amplifier mediation circuit for validating one of the sub-array control circuits and for invalidating another of the sub-array control circuits to regulate control of the column sense amplifier.

Claim 16

Dependent Claim 137 words

A dynamic RAM comprising: (a) a plurality of sub-arrays, each sub-array including a plurality of memory cells, each of the memory cells being connected to a cross point between a word line and a bit line such that each sub-array includes a plurality of word lines and a plurality of bit lines; (b) a plurality of TAG blocks, each of the TAG blocks being connected to a corresponding one of the sub-arrays, for storing a TAG address for the corresponding sub-array and for receiving an X address; and (c) a plurality of X decoders, one of the X decoders provided for each of the sub-arrays, for decoding the X address and selecting the word line corresponding to the X address; each of the TAG blocks being located adjacent to the X decoder provided for the corresponding sub-array.

Claim 17

Dependent Claim 137 words

A dynamic RAM comprising: (a) a plurality of sub-arrays, each sub-array including a plurality of memory cells, each of the memory cells being connected to a cross point between a word line and a bit line such that each sub-array includes a plurality of word lines and a plurality of bit lines; (b) a plurality of TAG blocks, each of the TAG blocks being connected to a corresponding one of the sub-arrays, for storing a TAG address for the corresponding sub-array and for receiving an X address; and (c) a plurality of X decoders, one of the X decoders provided for each of the sub-arrays, for decoding the X address and selecting the word line corresponding to the X address; each of the TAG blocks being located adjacent to the X decoder provided for the corresponding sub-array.

Claim 18

Dependent Claim 32 words

A dynamic RAM as set forth in claim 13, wherein each of the sub-arrays is located outside of a region where the corresponding TAG block and the corresponding X decoder are located.

Claim 19

Dependent Claim 34 words

A dynamic RAM as set forth in claim 13, wherein the plurality of sub-arrays is located outside of a region where the plurality of TAG blocks and the plurality of X decoders are located.

Claim 20

Dependent Claim 30 words

A dynamic RAM as set forth in claim 13, wherein the bit lines included in each of the sub-arrays are laid out along a longitudinal leg of a semiconductor chip.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1999-11-19	2000-05-20	2000-11-19	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	2003-11-19	2004-05-20	2004-11-19	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	2007-11-19	2008-05-20	2008-11-19	$7700.00	Window Closed / Lapsed

Dynamic random access memory (DRAM) with cache and tag

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