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US5577219A
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Method and apparatus for preforming memory segment limit violation checks
Assignee: Intel Corp
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Filing: 1994-05-02
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Granted: 1996-11-19
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Expires: 2014-05-02
Abstract
Abstract A method and apparatus for determining if an effective address for a memory access in a computer processor is above an expand-down memory segment. The apparatus comprises a memory segment limit comparison circuit. The segment limit comparison circuit tests every memory access to determine if the memory access reaches above the top limit of an expand-down memory segment. The comparison circuit consists of an adder that adds an effective address of the memory access to an access -- size value. The access -- size value consists of the size of the memory access to be performed minus one in the low order bits and a series of "1" bits in the high order bits necessary to generate a carry if the memory access reaches above the top limit of the expand-down memory segment.
Inventors
- 👤 Mark Timko
- 👤 Scott D. Rodgers
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 16:32
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/34; G06F9/355; G06F12/00; G06F12/14; G06F12/1416; G06F12/1425; G06F12/1441
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
112 words
A method of testing if a memory access falls above a defined memory segment, said memory access having a memory access size, said method comprising the steps of: generating an effective address for said memory access; concatenating a set of high order bits onto said memory access size minus one to create an access -- size, said set of high order bits for propagating a carry bit from said access -- size if said effective address of said memory access reaches above said defined memory segment; adding said access -- size to said effective address; and signaling a segment limit violation if said carry bit is generated from said step of adding.
Claim 2
Independent Claim
112 words
A method of testing if a memory access falls above a defined memory segment, said memory access having a memory access size, said method comprising the steps of: generating an effective address for said memory access; concatenating a set of high order bits onto said memory access size minus one to create an access -- size, said set of high order bits for propagating a carry bit from said access -- size if said effective address of said memory access reaches above said defined memory segment; adding said access -- size to said effective address; and signaling a segment limit violation if said carry bit is generated from said step of adding.
Claim 3
Dependent Claim
73 words
The method of testing a memory access as claimed in claim 1 wherein said defined memory segment has a size of 64Kilobytes and said step of concatenating a set of high order bits comprises the substeps of: placing sixteen "1" bits into a sixteen most significant bits of said access -- size; and placing said size of said memory access minus one in a sixteen least significant bits of said access -- size.
Claim 4
Dependent Claim
74 words
The method of testing a memory access as claimed in claim 1 wherein said defined memory segment has a size of 4 Gigabytes and said step of concatenating a set of high order bits comprises the substeps of: placing sixteen "0" bits into a sixteen most significant bits of said access -- size; and placing said size of said memory access minus one in a sixteen least significant bits of said access -- size.
Claim 5
Dependent Claim
50 words
The method of testing a memory access as claimed in claim 1 wherein said step of concatenating a set of high order bits comprises inverting a memory segment size bit and placing said inverted memory segment size bit value into a sixteen most significant bits of said access -- size.
Claim 6
Dependent Claim
27 words
The method of testing a memory access as claimed in claim 4 wherein said memory segment size bit comprises a D-bit in an Intel® Architecture compatible microprocessor.
Claim 7
Dependent Claim
53 words
The method of testing a memory access as claimed in claim 1 wherein said step of generating an effective address for said memory access comprises the substeps of multiplying an index by a scale to generate a product; and adding said product, a base address, and a displacement to create said effective address.
Claim 8
Independent Claim
132 words
An apparatus for testing if a memory access falls above a defined memory segment, said apparatus comprising the elements of: an effective address calculator for generating an effective address for a memory access into a memory segment; an access size register, said access size register for storing a size of a memory access minus one; an adder coupled to said effective address calculator and said access size register for adding said effective address and said size of said memory access minus one; and a most significant bit generator coupled to said access size register, said most significant bit generator for filling said access size register with bits such that said adder will propagate a carry from a most significant bit of said adder if said memory access reaches above said memory segment.
Claim 9
Independent Claim
132 words
An apparatus for testing if a memory access falls above a defined memory segment, said apparatus comprising the elements of: an effective address calculator for generating an effective address for a memory access into a memory segment; an access size register, said access size register for storing a size of a memory access minus one; an adder coupled to said effective address calculator and said access size register for adding said effective address and said size of said memory access minus one; and a most significant bit generator coupled to said access size register, said most significant bit generator for filling said access size register with bits such that said adder will propagate a carry from a most significant bit of said adder if said memory access reaches above said memory segment.
Claim 10
Dependent Claim
28 words
The apparatus for testing a memory access as claimed in claim 7 wherein said most significant bit generator comprises an inverter coupled to a memory segment size bit.
Claim 11
Dependent Claim
29 words
The apparatus for testing a memory access as claimed in claim 8 wherein said inverter is further coupled to the sixteen most significant bits of said access size register.
Claim 12
Dependent Claim
47 words
The apparatus for testing a memory access as claimed in claim 7 wherein said most significant bit generator fills said upper sixteen bits of said access size register and said size of a memory access minus one fills a lower sixteen bits of said access size register.
Claim 13
Dependent Claim
23 words
The apparatus for testing a memory access as claimed in claim 7 wherein said apparatus is implemented in an Intel® Architecture compatible microprocessor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-19 | 2000-05-20 | 2000-11-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-19 | 2004-05-20 | 2004-11-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-19 | 2008-05-20 | 2008-11-19 | $7700.00 | Window Closed / Lapsed |