Address boundary detector

Claim 1

A data processing system including means for detecting memory address page crossing, said system comprising, a memory for storing data in storage space divided into pages of 2 n storage locations per page, each of said locations being specified by a multi-bit binary address such that the least significant n bits of said address identify one of said locations within a particular page and the remaining bits of said address identify the particular page containing said one location, an integrated circuit arithmetic unit for performing the addition of a base addend address to an offset addend address to form a result address, said arithmetic unit including means for adding the nth bit of the base addend address, the nth bit of the offset addend address, and the low-order carry bit resulting from the addition of the --1 lower order bits of the two addend addresses to generate a result bit and a boundary crossing carry bit, said boundary crossing carry bit being inaccessible to circuitry exterior to said integrated circuit arithmetic unit, and a sensing mechanism external to said integrated circuit for generating a replica of said boundary crossing carry bit to identify result addresses which specify a memory location in a page different than the page occupied by the location specified by said base addend address, said sensing mechanism comprising, in combination, a first input connected to receive said low-order carry bit, a second input connected to receive the nth bit of one of said addend addresses, a third input connected to receive said result bit, and first logic means responsive to the bit values received on said first, second and third inputs for generating said replica of said boundary crossing carry bit, said replica being a binary 1 whenever a binary 0 is received at said third input and a binary 1 is received at either said first or said second input, or a binary 1 is received at both said first and second inputs.