Semiconductor memory device having a variably write pulse width capability

Claim 1

A semiconductor memory device equipped with a write control system for controlling data write to a selected memory cell on the basis of a write control signal, comprising: an external terminal for test; and a write-pulse generating circuit for generating a test write pulse on the basis of a set signal applied thereto from said external terminal and said write control signal, and supplying said test write pulse to said write control system; said write pulse generating circuit including a pulse-width changing circuit for variably setting the pulse width of said test write pulse on the basis of said set signal, wherein said pulse-width changing circuit includes a delay circuit which comprises a plurality of gates each having a delay time and connected in multiple stages, and the gate of the initial stage of which responds to said write control signal, and a shift register having a multiple-bit structure wherein the output terminal of each bit is connected to the input terminals of specific gates of a plurality of said gates, and wherein a total delay time in said delay circuit is variably set to a quantity corresponding to a desired write pulse width by inputting said set signal to said shift register in a specific manner, wherein said shift register includes an inverter and a plurality of cascaded RS flip-flops in a number corresponding to the plurality of said bits, said flip-flop of the initial stage being reset by said set signal and set by the output of said inverter, and the output terminal of each of said flip-flops is connected to the corresponding input terminal of each of said specific gates.