Process for fabricating static random access memory having stacked transistors

Claim 1

A process for fabricating memory cells of a static random access memory (SRAM) device having a plurality of memory cells formed on a semiconductor substrate, each of said SRAM memory cells includes: a first MOS transistor having one of a drain/source pair thereof coupled to a first voltage for said SRAM device; a second MOS transistor having one of the drain/source pair thereof coupled to said first voltage, the other of the drain/source pair thereof being coupled to the gate of said first MOS transistor and forming a second node, and the gate of said second MOS transistor being coupled to the other of said drain/source pair of said first MOS transistor and forming a first node; a first resistor coupled to said first node at one end and to a second voltage at the other; a second resistor coupled to said second node at one end and to said second voltage at the other; a third MOS transistor having drain/source pair coupled to said first node and a first bit line, and a gate thereof coupled to a word line, respectively; and a fourth MOS transistor having a pair of drain/source coupled to said second node and a second bit line, and gate thereof coupled to said word line, respectively; wherein said process comprises: forming said first and second MOS transistors on said semiconductor substrate; forming said first and second resistors over said first and second MOS transistors, respectively; forming said third and fourth MOS transistors and said word line over said first and second resistors, and forming said first and second bit lines over said third and fourth MOS transistors, respectively.