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US5574945A
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Multi channel inter-processor coupling facility processing received commands stored in memory absent status error of channels
Assignee: International Business Machines Corp
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Filing: 1995-06-07
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Granted: 1996-11-12
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Expires: 2015-06-07
Abstract
Abstract A computer system with a coupling facility is provided with a plurality of processors and a plurality of intersystem channels coupled to the processors via a memory bus. The coupling facility includes a memory bus interface for the memory bus and a plurality of channels for coupling said channels to said processors. The memory bus interface includes an adapter with at least two hardware vectors provided for command detection, command isolation, and parallel testing of the error states of the intersystem channels, one which detects a command vector arrival, and a second which contains error state vector indicators. A LOCATE CHANNEL BUFFER (LCB) instruction is employed which performs a sense and reset operation on the command vector to identify and isolate a new command, and subsequently reads a vector of said error states vector indicator to determine the presence or absence of link errors.
Inventors
- 👤 David A. Elko
- 👤 Gottfried A. Goldrian
- 👤 Steven N. Goss
- 👤 Thomas A. Gregg
- 👤 Audrey A. Helffrich
- 👤 Ambrose A. Verdibello, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-28 23:01
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141; G06F11/0703; G06F11/0706; G06F11/0721; G06F11/0724; G06F11/073; G06F11/0766; G06F11/0772
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
184 words
A computer system interface apparatus, comprising: a coupling facility comprising: a plurality of intersystem channels programmable to receive one or more commands from one or more central processing complexes coupled to said coupling facility; a memory for storing said one or more commands received by said plurality of intersystem channels; a memory bus adapter providing an interface between said plurality of intersystem channels and said memory, said memory bus adapter providing a central location for storing state information, said state information indicating whether any of said plurality of intersystem channels has an error and whether any of said one or more commands is stored in said memory; and at least one processor coupled to said memory bus adapter and said memory, said at least one processor programmable to poll said state information to determine when said one or more commands is stored in said memory and whether any errors exist, said at least one processor programmable to process said one or more commands when said one or more commands is stored in said memory and no errors exist on said plurality of intersystem channels.
Claim 2
Dependent Claim
184 words
A computer system interface apparatus, comprising: a coupling facility comprising: a plurality of intersystem channels programmable to receive one or more commands from one or more central processing complexes coupled to said coupling facility; a memory for storing said one or more commands received by said plurality of intersystem channels; a memory bus adapter providing an interface between said plurality of intersystem channels and said memory, said memory bus adapter providing a central location for storing state information, said state information indicating whether any of said plurality of intersystem channels has an error and whether any of said one or more commands is stored in said memory; and at least one processor coupled to said memory bus adapter and said memory, said at least one processor programmable to poll said state information to determine when said one or more commands is stored in said memory and whether any errors exist, said at least one processor programmable to process said one or more commands when said one or more commands is stored in said memory and no errors exist on said plurality of intersystem channels.
Claim 3
Dependent Claim
58 words
A computer system interface apparatus according to claim 1 wherein said memory bus adapter comprises a first hardware vector to store error state vector indicators specifying whether any of said plurality of intersystem channels has an error, and a second hardware vector to store command active indicators specifying storage of said one or more commands in said memory.
Claim 4
Dependent Claim
56 words
A computer system interface apparatus according to claim 2, further comprising means for executing a LOCATE CHANNEL BUFFER (LCB) instruction to perform a sense and reset operation on said second hardware vector to identify and isolate a new command, and subsequently to read said first hardware vector to determine the presence or absence of said error(s).
Claim 5
Dependent Claim
41 words
A computer system interface apparatus according to claim 3 wherein when said error(s) are present, LCB restores one of said command active indicators and an error condition code is provided to a coupling facility control program executing within said coupling facility.
Claim 6
Dependent Claim
35 words
A computer system interface apparatus according to claim 3 wherein when none of said error(s) are present, LCB returns an identity of an isolated command to the coupling facility which can complete a dispatch operation.
Claim 7
Dependent Claim
35 words
A computer system interface apparatus according to claim 3, further comprising means for executing a coupling facility control program to identify and to isolate newly arrived commands and simultaneously detect an absence of said error(s).
Claim 8
Dependent Claim
37 words
A computer system interface apparatus according to claim 3 wherein a round-robin scan of the memory bus adapter is performed under a microprogram control for detecting command arrival to prevent biasing of service to particular intersystem channels.
Claim 9
Dependent Claim
25 words
A computer system interface apparatus according to claim 3 wherein a microcode program is provided for said memory bus adapter which executes the LCB instruction.
Claim 10
Dependent Claim
73 words
A computer system interface apparatus according to claim 3 wherein a microcode program is provided for said memory bus adapter which executes the LCB instruction, wherein initially a sense command is sent to said memory bus adapter to fetch said second hardware vector and wherein bits for channel buffers that are not available to the coupling facility are masked off, and a resulting vector is searched to find a bit that is set.
Claim 11
Dependent Claim
123 words
A computer system interface apparatus according to claim 2, wherein said coupling facility further comprises a memory bus providing an interface between said at least one processor and said memory bus adapter, and wherein said memory bus adapter further comprises a memory bus send register coupled to said memory bus, a memory bus receive register coupled to said memory bus, a sense/control command register coupled to said memory bus receive register, a sense/control state machine including an arbiter coupled to said sense/control command register, a bit modifier command register providing an interface between one of said plurality of intersystem channels and the sense/control state machine, and a vector bit modifier coupled to said sense/control state machine and said first and second hardware vectors.
Claim 12
Dependent Claim
81 words
A computer system interface apparatus according to claim 10, further comprising means for executing a processor program to issue a sense and reset command on said memory bus adapter, said sense and reset command including a vector selection of said first hardware vector or said second hardware vector, a bit index within said first hardware vector, and a modification order to either set a bit or reset the bit in said first or second hardware vector selected by said vector selection.
Claim 13
Dependent Claim
47 words
A computer system interface apparatus according to claim 2 wherein a dispatcher program is included with means for allowing for efficient lookup procedures by the dispatcher program by storing a token when a channel buffer is prepared and returning the token when a command arrival is reported.
Claim 14
Dependent Claim
32 words
A computer system interface apparatus according to claim 3 wherein said memory bus adapter is provided with access to said memory, said memory providing read-only areas and processor-specific fields for LCB functioning.
Claim 15
Dependent Claim
69 words
A computer system interface apparatus according to claim 1 wherein said one or more commands is transmitted between said plurality of intersystem channels-and said at least one processor and when an error state pending indicia located in said memory bus adapter is on, one of said at least one processor must complete handling of the error before any other command will be processed by said at least one processor.
Claim 16
Dependent Claim
46 words
A computer system interface apparatus according to claim 1 wherein said one or more commands is transmitted between said plurality of intersystem channels and said at least one processor and when an error is indicated execution of any of said one or more commands is delayed.
Claim 17
Dependent Claim
73 words
A computer system interface apparatus according to claim 1 wherein said one or more commands is transmitted between said plurality of intersystem channels and said at least one processor and when an error is indicated execution of any of said one or more commands is delayed, and a logic flow will locate one of said plurality of intersystem channels with an active command, or set an indicator showing that said error is present.
Claim 18
Dependent Claim
68 words
A computer system interface apparatus according to claim 1 wherein said one or more commands is transmitted between said plurality of intersystem channels and said at least one processor and wherein state machine control logic controls an interface between one of said at least one processor and one of said plurality of intersystem channels, and selects a vector and conditionally sets or resets an indicator in said vector.
Claim 19
Dependent Claim
69 words
A computer system interface apparatus according to claim 1 wherein said one or more commands is transmitted between said plurality of intersystem channels and said at least one processor and wherein a locate channel buffer instruction is employed to provide an active command or set an indicator showing that there was no error in a link, in the event that an error had been indicated and was not present.
Claim 20
Dependent Claim
84 words
A computer system interface apparatus according to claim 1 wherein said one or more commands is transmitted between said plurality of intersystem channels and said at least one processor and wherein means are provided for isolating a command to one of said at least one processor, including a vector associated with every intersystem channel of said plurality of intersystem channels, a mask applied to a vector to show an intersystem channel assignment, where logical partitioning of a processor grouping is controlled by the mask.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-12 | 2000-05-13 | 2000-11-12 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-12 | 2004-05-13 | 2004-11-12 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-12 | 2008-05-13 | 2008-11-12 | $7700.00 | Window Closed / Lapsed |