Multi-channel/multi-circuit communication controller

Claim 2

A multi-channel communication controller for use with a main computer utilizing a plurality of channels, the controller comprising: a plurality of subprocessor sections, each subprocessor section disposed for an associated channel of the plurality of channels to conduct communication processing, each said subprocessor section including a subprocessor CPU, a subprocessor RAM, a subprocessor serial controller connected to the associated channel, a subprocessor local bus for establishing connections in each said subprocessor between said subprocessor CPU, said subprocessor RAM, and said subprocessor serial controller, and a subprocessor controller connected to said subprocessor local bus; a main processor section for controlling said subprocessor sections, said main processor section including a main CPU, a main ROM, a main RAM, a main local bus for establishing connections between said main CPU, said main ROM, and said main RAM, and a main controller connected to said main local bus; an upper-level local bus connected to said main controller and each of the subprocessor controllers; and, a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of the main computer, said memory sharing section including a shared controller connected to said upper-level local bus and said system bus and a shared RAM connected to said shared controller, wherein each said subprocessor controller includes an address translating section for accomplishing an address translation on an address supplied from said main processor section via said upper-level local bus so as to transfer an address after the address translation to said RAM associated thereto.

Claim 3

The multi-channel communication controller according to claim 1, wherein: said shared RAM includes means for storing therein a plurality of communication programs; and said main processor section includes means for selectively transferring the plurality of communication programs from said shared memory to said subprocessor RAMs.

Claim 4

The multi-channel communication controller according to claim 2, wherein said plurality of communication programs include means for executing different communication protocols.

Claim 5

The multi-channel communication controller according to claim 1, wherein each said subprocessor controller includes an initiation flag for causing an interruption to its own subprocessor section in response to an initiation from other of processor sections and a report flag for causing another interruption from its own subprocessor section to the other said processor sections.

Claim 6

The multi-channel communication controller according to claim 1, wherein at least one of said subprocessor controllers and said main controller includes tables of an identical format containing at least one of an initiation command kind from said system processor section, a sequence of the command, an identifier of a command object, a pointer denoting a related area in said shared memory, and a data length thereof.

Claim 7

The multi-channel communication controller according to claim 1, wherein said multi-channel communication controller is fabricated in a communication adapter board.

Claim 8

The multi-channel communication controller according to claim 1, wherein each said subprocessor controller includes means for directly writing received communication data in a predetermined reception buffer area of said shared memory.

Claim 9

The multi-channel communication controller according to claim 1, wherein in each said subprocessor section, at least said subprocessor CPU, said subprocessor serial controller, said subprocessor local bus, and said subprocessor controller are fabricated in a one-chip microcomputer.

Claim 10

The multi-channel communication controller according to claim 8, wherein each said subprocessor section is fabricated in an identical one-chip microcomputer and the address translating section in said subprocessor controller includes means for responding to a setting of a control signal from an external device to set an address translation value thereof to a value different from values of other subprocessors.

Claim 11

The multi-channel communication controller according to claim 1, further comprising a speed matching section connected to said serial controllers in said subprocessor sections and said main processor section for changing, under control of said main processor section, transmission speed in a communication between each said subprocessor section and an external device.

Claim 12

A multi-channel communication controller for use with a main computer utilizing a plurality of channels, the controller comprising: a plurality of subprocessor sections, each subprocessor section disposed for an associated channel of the plurality of channels to conduct communication processing, each said subprocessor section including a subprocessor CPU, a subprocessor serial controller, a subprocessor local bus for establishing connections between said subprocessor CPU and said subprocessor serial controller, and a subprocessor controller connected to said local bus; a main processor section for controlling said subprocessor sections, said main processor section including a main CPU, a main ROM, a main RAM, a main local bus for establishing connections between said main CPU, said main ROM, and said main RAM, and a main controller connected to said main local bus; an upper-level local bus connected to said main controller and each of the subprocessor controllers; and, a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of the main computer, said memory sharing section including a shared controller connected to said upper-level local bus and said system bus and a shared RAM connected to said shared controller, wherein each said subprocessor controller includes an address translating section for accomplishing an address translation on an address outputted from said CPU of said subprocessor section so as to transfer an address after the translation to said upper-level local bus.

Claim 13

A multi-channel communication controller for use with a main computer utilizing a plurality of channels, the controller comprising: a plurality of subprocessor sections, each subprocessor section disposed for an associated channel of the plurality of channels to conduct communication processing, each said subprocessor section including a subprocessor CPU, a subprocessor serial controller, a subprocessor local bus for establishing connections between said subprocessor CPU and said subprocessor serial controller, and a subprocessor controller connected to said local bus; a main processor section for controlling said subprocessor sections, said main processor section including a main CPU, a main ROM, a main RAM, a main local bus for establishing connections between said main CPU, said main ROM, and said main RAM, and a main controller connected to said main local bus; an upper-level local bus connected to said main controller and each of the subprocessor controllers; and, a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of the main computer, said memory sharing section including a shared controller connected to said upper-level local bus and said system bus and a shared RAM connected to said shared controller, wherein each said subprocessor controller includes an address translating section for accomplishing an address translation on an address outputted from said CPU of said subprocessor section so as to transfer an address after the translation to said upper-level local bus.

Claim 14

The multi-channel communication controller according to claim 11, wherein: said shared RAM includes means for storing therein a plurality of communication programs; and each of said main processor and subprocessor sections includes means for selectively accessing the plurality of communication programs in said shared memory to execute the plurality of communication programs.

Claim 15

The multi-channel communication controller according to claim 12, wherein said plurality of communication programs include means for executing different communication protocols.

Claim 16

The multi-channel communication controller according to claim 11, wherein each said subprocessor controller includes an initiation flag for causing an interruption to its own subprocessor section in response to an initiation from other processor processors sections and a report flag for causing another interruption from its own subprocessor section to the other processor sections.

Claim 17

The multi-channel communication controller according to claim 11, wherein said multi-channel communication controller is fabricated in a communication adapter board.

Claim 18

The multi-channel communication controller according to claim 11, wherein each said subprocessor controller includes means for directly writing received communication data in a predetermined reception buffer area of said shared memory.

Claim 19

The multi-channel communication controller according to claim 11, wherein in each said subprocessor section, at least said subprocessor CPU, said subprocessor serial controller, said subprocessor local bus, and said subprocessor controller are constituted in a one-chip microcomputer.

Claim 20

The multi-channel communication controller according to claim 17, wherein said each subprocessor section is configured in an identical one-chip micro-computer and the address translation section in said subprocessor controller includes means for responding to a setting of a control signal from an external device to set an address translation value thereof to a value different from values of other subprocessors.

Claim 21

The multi-channel communication controller according to claim 11, further comprising a speed matching section connected to said serial controllers in said subprocessor sections and said main processor section for changing, under control of said main processor section, transmission speed in a communication between each said subprocessor section and an external device.

Claim 22

A multi-channel communication controller according to claim 11, wherein each said controller includes a table of an identical format containing at least one of a kind of an initiation command from said system processor section, a sequence of the command, an identifier of a command object, a pointer denoting a related area in said shared memory, and a data length thereof.

Claim 23

An ISDN communication controller for use in a main computer, the controller comprising: a first subprocessor section for achieving communication processing on B channels, said first subprocessor section including a first CPU, a first RAM, a first serial controller connected to the B channels, a first local bus for establishing connections between said first CPU, said first RAM, and said first serial controller, and a first controller connected to said first local bus; a second subprocessor section for achieving communication processing on the B channels, said second subprocessor section including a second CPU, a second RAM, a second serial controller connected to the B channels, a second local bus for establishing connections between said second CPU, said second RAM, and said second serial controller, and a second controller connected to said second local bus; an LAPD processing section for achieving communication processing on a D channel, said LAPD processing section including a third CPU, a first ROM, a third serial controller connected to the D channel, a third local bus for establishing connections between said third CPU, said first ROM, and said third serial controller, and a third controller connected to said third local bus; a main processor section for controlling said first and second subprocessor sections and said LAPD processing section, said main processor section including a fourth CPU, a second ROM, a third RAM, a fourth local bus for establishing connections between said fourth CPU, said second ROM, said third RAM, and said fourth local bus, and a fourth controller connected to said fourth local bus; an upper-level local bus connected to said first, second, and fourth controllers; a line driver for multiplexing an ISDN line into the D and B channels, said D channel being connected to said third serial controller; a channel control section connected to said line driver, said first and second subprocessor sections, and said fourth local bus for operating under control of said main processor to connect said B channels to said first and second serial controllers such that said B channels can be changed over between said first and second controllers; and a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of said main computer, said memory sharing section including a controller connected to said upper-level local bus and said system bus and a shared RAM connected to said controller, wherein: said first controller includes a first address translating section for achieving a first address translation on a first address supplied from said main processor section via said upper-level local bus to transfer a first translated address after the first address translation to said first RAM; and said second controller includes a second address translating section for achieving a second address translation on a second address supplied from said main processor section via said upper-level local bus to transfer a second translated address after the second address translation to said second RAM.

Claim 24

An ISDN communication controller for use in a main computer, the controller comprising: a first subprocessor section for achieving communication processing on B channels, said first subprocessor section including a first CPU, a first RAM, a first serial controller connected to the B channels, a first local bus for establishing connections between said first CPU, said first RAM, and said first serial controller, and a first controller connected to said first local bus; a second subprocessor section for achieving communication processing on the B channels, said second subprocessor section including a second CPU, a second RAM, a second serial controller connected to the B channels, a second local bus for establishing connections between said second CPU, said second RAM, and said second serial controller, and a second controller connected to said second local bus; an LAPD processing section for achieving communication processing on a D channel, said LAPD processing section including a third CPU, a first ROM, a third serial controller connected to the D channel, a third local bus for establishing connections between said third CPU, said first ROM, and said third serial controller, and a third controller connected to said third local bus; a main processor section for controlling said first and second subprocessor sections and said LAPD processing section, said main processor section including a fourth CPU, a second ROM, a third RAM, a fourth local bus for establishing connections between said fourth CPU, said second ROM, said third RAM, and said fourth local bus, and a fourth controller connected to said fourth local bus; an upper-level local bus connected to said first, second, and fourth controllers; a line driver for multiplexing an ISDN line into the D and B channels, said D channel being connected to said third serial controller; a channel control section connected to said line driver, said first and second subprocessor sections, and said fourth local bus for operating under control of said main processor to connect said B channels to said first and second serial controllers such that said B channels can be changed over between said first and second controllers; and a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of said main computer, said memory sharing section including a controller connected to said upper-level local bus and said system bus and a shared RAM connected to said controller, wherein: said first controller includes a first address translating section for achieving a first address translation on a first address supplied from said main processor section via said upper-level local bus to transfer a first translated address after the first address translation to said first RAM; and said second controller includes a second address translating section for achieving a second address translation on a second address supplied from said main processor section via said upper-level local bus to transfer a second translated address after the second address translation to said second RAM.

Claim 25

The ISDN communication controller according to claim 21, wherein: said shared RAM includes means for storing therein a plurality of communication programs; and, said main processor section including means for selectively transferring the plurality of communication programs to said RAMs of said subprocessor sections.

Claim 26

The ISDN communication controller according to claim 22, wherein said plurality of communication programs include means for executing different communication protocols.

Claim 27

The ISDN communication controller according to claim 21, wherein each said controller in said subprocessor sections includes an initiation flag for causing an interruption in its own subprocessor section in response to an initiation from other processor sections and a report flag for causing another interruption from its own subprocessor section to the other processor sections.

Claim 28

The ISDN communication controller according to claim 21, wherein each of said controllers includes a table of an identical format containing at least one of an initiation command kind from said system processor section, a sequence of the command, an identifier of a command object, a pointer denoting a related area in said shared memory, and a data length thereof.

Claim 29

The ISDN communication controller according to claim 21, wherein said multi-channel communication controller is fabricated in a communication adapter board.

Claim 30

The ISDN communication controller according to claim 21, wherein each said controller in said subprocessor sections includes means for directly writing received communication data in a predetermined reception buffer area of said shared memory.

Claim 31

The ISDN communication controller according to claim 21, wherein in each said subprocessor section, at least said CPU, said serial controller, said local bus, and said controller are constituted in a one-chip microcomputer.

Claim 32

The ISDN communication controller according to claim 28, wherein each said subprocessor section is fabricated in an identical one-chip microcomputer and the address translation section in each said controller includes means for responding to a setting of a control signal from an external device to set an address translation value thereof to a value different from values of other subprocessor.

Claim 33

The ISDN communication controller according to claim 21, further comprising a speed matching section connected to said serial controllers in said subprocessor sections and said main processor section for changing, under control of said main processor section, transmission speed in a communication between each said subprocessor section and an external device.

Claim 34

An ISDN communication controller for use in a main computer, the controller comprising: a first subprocessor section for achieving communication processing on B channels, said first subprocessor section including a first CPU, a first serial controller connected to the B channels, a first local bus for establishing connections between said first CPU and said first serial controller, and a first controller connected to said first local bus; a second subprocessor section for achieving communication processing on the B channels, said second subprocessor section including a second CPU, a second serial controller connected to the B channels, a second local bus for establishing connections between said second CPU and said second serial controller, and a second controller connected to said second local bus; an LAPD processing section for achieving communication processing on a D channel, said LAPD processing section including a third CPU, a first ROM, a third serial controller connected to the D channel, a third local bus for establishing connections between said third CPU, said first ROM, and said third serial controller, and a third controller connected to said third local bus; a main processor section for controlling said first and second subprocessor sections and said LAPD processing section, said main processor section including a fourth CPU, a second ROM, an RAM, a fourth local bus for establishing connections between said fourth CPU, said second ROM, said RAM, and said fourth local bus, and a fourth controller connected to said fourth local bus; an upper-level local bus connected to said first, second, and fourth controllers; a line driver for multiplexing an ISDN line into the D and B channels, said D channel being connected to said third serial controller; a channel control section connected to said line driver, said first and second subprocessor sections, and said fourth local bus for operating under control of said main processor to connect said B channels to said first and second serial controllers such that said B channels can be changed over between said first and second controllers; and a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of said main computer, said memory sharing section including a controller connected to said upper-level local bus and said system bus and a shared RAM connected to said controller, wherein: said first controller includes a first address translating section for achieving a first address translation on a first address supplied from said first CPU via said upper-level local bus to transfer a first translated address after the first translation to said shared RAM; and said second controller includes a second address translating section for achieving a second address translation on a second address supplied from said second CPU via said upper-level local bus to transfer a second translated address after the second translation to said shared RAM.

Claim 35

An ISDN communication controller for use in a main computer, the controller comprising: a first subprocessor section for achieving communication processing on B channels, said first subprocessor section including a first CPU, a first serial controller connected to the B channels, a first local bus for establishing connections between said first CPU and said first serial controller, and a first controller connected to said first local bus; a second subprocessor section for achieving communication processing on the B channels, said second subprocessor section including a second CPU, a second serial controller connected to the B channels, a second local bus for establishing connections between said second CPU and said second serial controller, and a second controller connected to said second local bus; an LAPD processing section for achieving communication processing on a D channel, said LAPD processing section including a third CPU, a first ROM, a third serial controller connected to the D channel, a third local bus for establishing connections between said third CPU, said first ROM, and said third serial controller, and a third controller connected to said third local bus; a main processor section for controlling said first and second subprocessor sections and said LAPD processing section, said main processor section including a fourth CPU, a second ROM, an RAM, a fourth local bus for establishing connections between said fourth CPU, said second ROM, said RAM, and said fourth local bus, and a fourth controller connected to said fourth local bus; an upper-level local bus connected to said first, second, and fourth controllers; a line driver for multiplexing an ISDN line into the D and B channels, said D channel being connected to said third serial controller; a channel control section connected to said line driver, said first and second subprocessor sections, and said fourth local bus for operating under control of said main processor to connect said B channels to said first and second serial controllers such that said B channels can be changed over between said first and second controllers; and a memory sharing section connected to said upper-level local bus and to a system bus of a system processor section for supervising control of said main computer, said memory sharing section including a controller connected to said upper-level local bus and said system bus and a shared RAM connected to said controller, wherein: said first controller includes a first address translating section for achieving a first address translation on a first address supplied from said first CPU via said upper-level local bus to transfer a first translated address after the first translation to said shared RAM; and said second controller includes a second address translating section for achieving a second address translation on a second address supplied from said second CPU via said upper-level local bus to transfer a second translated address after the second translation to said shared RAM.

Claim 36

The ISDN communication controller according to claim 31, wherein: said shared RAM includes means for storing therein a plurality of communication programs; and each of said main processor and subprocessor sections includes means for selectively accessing the plurality of communication programs in said shared memory to execute the plurality of communication programs.

Claim 37

The ISDN communication controller according to claim 32, wherein said plurality of communication programs includes means for executing different communication protocols.

Claim 38

The ISDN communication controller according to claim 31, wherein each said controller in said subprocessor sections includes an initiation flag for causing an interruption in its own subprocessor section in response to an initiation from other processor sections and a report flag for causing another interruption from its own subprocessor section into the other processor sections.

Claim 39

The ISDN communication controller according to claim 31, wherein each of said controllers includes a table of an identical format containing at least one of an initiation command kind from said system processor section, a sequence of the command, an identifier of a command object, a pointer denoting a related area in said shared memory, and a data length thereof.

Claim 40

The ISDN communication controller according to claim 31, wherein said ISDN communication controller is fabricated in a communication adapter board.

Claim 41

The ISDN communication controller according to claim 31, wherein each said controller in said subprocessor sections includes means for directly writing received communication data in a predetermined reception buffer area of said shared memory.

Claim 42

The ISDN communication controller according to claim 31, wherein in each said subprocessor section, at least said CPU, said serial controller, said local bus, and said controller are constituted in a one-chip microcomputer.

Claim 43

The ISDN communication controller according to claim 38, wherein said each subprocessor section is fabricated in an identical one-chip microcomputer and the address translating section in each said controller includes means for responding to a setting of a control signal from an external device to set an address translation value thereof to a value different from values of other subprocessors.

Claim 44

The ISDN communication controller according to claim 31, further comprising a speed matching section connected to said serial controllers in said subprocessor sections and said main processor section for changing, under control of said main processor section, transmission speed in a communication between each said subprocessor section and an external device.