Patent US5572680A successfully refreshed from Google Patents.
US5572680A
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Method and apparatus for processing and transferring data to processor and/or respective virtual processor corresponding to destination logical processor number
Assignee: Fujitsu Ltd
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Filing: 1993-08-20
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Granted: 1996-11-05
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Expires: 2013-08-20
Abstract
Abstract In a multiprocessor system, transfer processing sections permit transfer of data and system information among a plurality of processors in order for the processors to perform parallel processing. The system includes physical processors within which virtual processors are realized and a plurality of logical processors corresponding to a plurality of processes to be processed. In transferring data and system information, each of the transfer processing sections selects a destination logical process number corresponding to a process to be transferred and reads from main storage physical processor and within-physical-processor virtual processor numbers corresponding to the logical processor number, data and system information for transfer toward a destination. In the destination, the physical or virtual processor executes the process.
Inventors
- 👤 Masayuki Ikeda
- 👤 Shigeru Nagasawa
- 👤 Naoki Shinjo
- 👤 Teruo Utsumi
- 👤 Masami Dewa
- 👤 Haruhiko Ueno
- 👤 Kazushige Kobayakawa
- 👤 Kenichi Ishizaka
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 14:14
CPC Classifications
G; G06; G06F; G06F15/00; G06F15/16; G06F15/163; G06F15/17
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
194 words
A virtual processor system comprising: a plurality of processor to execute processes in parallel including respective virtual processors and storing a plurality of logical processor numbers corresponding to destination processors of said plurality of processors; main storage means, associated with said plurality of processors for storing data and system information; and transfer processing means for transferring said data and system information among said plurality of processors by selecting a destination logical processor number of said plurality of logical processor numbers corresponding to a processor and a respective virtual processor of said plurality of processors, reading said data and system information from said main storage together with said processor and said respective virtual processor corresponding to said selected destination logical processor number and transferring said read data and system information to at least one of said processor and said respective virtual processor; wherein said transfer processing means associates said destination logical processor number with a physical processor valid flag, and when said physical processor valid flag indicates an invalid state, cancels communication of data designating the processor and, when said physical processor valid flag indicates a valid state, starts communication of data designating the processor.
Claim 2
Dependent Claim
194 words
A virtual processor system comprising: a plurality of processor to execute processes in parallel including respective virtual processors and storing a plurality of logical processor numbers corresponding to destination processors of said plurality of processors; main storage means, associated with said plurality of processors for storing data and system information; and transfer processing means for transferring said data and system information among said plurality of processors by selecting a destination logical processor number of said plurality of logical processor numbers corresponding to a processor and a respective virtual processor of said plurality of processors, reading said data and system information from said main storage together with said processor and said respective virtual processor corresponding to said selected destination logical processor number and transferring said read data and system information to at least one of said processor and said respective virtual processor; wherein said transfer processing means associates said destination logical processor number with a physical processor valid flag, and when said physical processor valid flag indicates an invalid state, cancels communication of data designating the processor and, when said physical processor valid flag indicates a valid state, starts communication of data designating the processor.
Claim 3
Dependent Claim
27 words
A system according to claim 1, wherein said processors execute processes differing from said process in a transfer requesting processor during said data and system information transfer.
Claim 4
Dependent Claim
68 words
A system according to claim 1, wherein said transfer processing means associates said destination logical processor number with said processor, said respective virtual processor and a within-physical-processor virtual processor valid flag, and, when said virtual processor valid flag indicates an invalid state, cancels communication of data designating the processor and, when said virtual processor valid flag indicates a valid state, starts communication of data designating the virtual processor.
Claim 5
Dependent Claim
190 words
A data transferring device comprising: a plurality of processors each having a data storage and performing predetermined processing; and communication means for permitting transfer of data and system information among said plurality of processors, each of said plurality of processors including: system information storage means for storing access information for data transfer associated with said data, said access information including process identification data for identifying a group of said plurality of processors to execute a program and a destination logical processor number; a plurality of processor translating means for translating said destination logical processor numbers stored in said system information storage means to physical processors and virtual processors in correspondence with said process identification data; and transfer control means, responsive to said physical and virtual processors translated by said processor translating means, for reading data from said data storage and transferring said read data with said access information to at least one of said physical and virtual processors; wherein said transfer control means performs data transfer processing using a packet having a header including said physical processor, said virtual processor, said access information, and body data associated with said header.
Claim 6
Dependent Claim
190 words
A data transferring device comprising: a plurality of processors each having a data storage and performing predetermined processing; and communication means for permitting transfer of data and system information among said plurality of processors, each of said plurality of processors including: system information storage means for storing access information for data transfer associated with said data, said access information including process identification data for identifying a group of said plurality of processors to execute a program and a destination logical processor number; a plurality of processor translating means for translating said destination logical processor numbers stored in said system information storage means to physical processors and virtual processors in correspondence with said process identification data; and transfer control means, responsive to said physical and virtual processors translated by said processor translating means, for reading data from said data storage and transferring said read data with said access information to at least one of said physical and virtual processors; wherein said transfer control means performs data transfer processing using a packet having a header including said physical processor, said virtual processor, said access information, and body data associated with said header.
Claim 7
Independent Claim
179 words
A method for permitting a plurality of processors to perform parallel processing by permitting transfer of data and system information among said processors which have respective virtual processors established within them and relate actual physical processors and said virtual processors to form a plurality of logical processors as a whole, said data transfer processing method comprising the steps of: storing access information for transferring of data including process identification data for identifying a group of said plurality of processes to execute a program and a destination logical processor number in system information storage; translating said destination logical processor number to a physical processor number and a virtual processor number in correspondence with said process identification data; and transferring data read from a data storage and said access information to at least one of physical and virtual processors in accordance with said physical and virtual processor numbers; wherein said transferring step performs data transfer processing using a packet having a header including said physical processor number, said virtual processor number, said access information, and body data associated with said header.
Claim 8
Independent Claim
179 words
A method for permitting a plurality of processors to perform parallel processing by permitting transfer of data and system information among said processors which have respective virtual processors established within them and relate actual physical processors and said virtual processors to form a plurality of logical processors as a whole, said data transfer processing method comprising the steps of: storing access information for transferring of data including process identification data for identifying a group of said plurality of processes to execute a program and a destination logical processor number in system information storage; translating said destination logical processor number to a physical processor number and a virtual processor number in correspondence with said process identification data; and transferring data read from a data storage and said access information to at least one of physical and virtual processors in accordance with said physical and virtual processor numbers; wherein said transferring step performs data transfer processing using a packet having a header including said physical processor number, said virtual processor number, said access information, and body data associated with said header.
Claim 9
Dependent Claim
175 words
A data transferring device comprising: a plurality of processor each having a data storage and performing predetermined processing; and communication means for permitting transfer of data and system information among said plurality of processors, each of said plurality of processors including: system information storage means for storing access information for data transfer associated with said data, said access information including destination logical processor numbers; a plurality of processor translating means for translating said destination logical processor numbers stored in said system information storage means to physical processor numbers and virtual processor numbers in correspondence with a process; and transfer control means, responsive to said physical and virtual processor numbers translated by said processor translating means, for reading data from said data storage means and transferring said read data with said access information to at least one of physical and virtual processors; wherein said transfer control means performs data transfer processing using a packet having a header including said physical processor number, said virtual processor number, said access information, and body data associated with said header.
Claim 10
Dependent Claim
175 words
A data transferring device comprising: a plurality of processor each having a data storage and performing predetermined processing; and communication means for permitting transfer of data and system information among said plurality of processors, each of said plurality of processors including: system information storage means for storing access information for data transfer associated with said data, said access information including destination logical processor numbers; a plurality of processor translating means for translating said destination logical processor numbers stored in said system information storage means to physical processor numbers and virtual processor numbers in correspondence with a process; and transfer control means, responsive to said physical and virtual processor numbers translated by said processor translating means, for reading data from said data storage means and transferring said read data with said access information to at least one of physical and virtual processors; wherein said transfer control means performs data transfer processing using a packet having a header including said physical processor number, said virtual processor number, said access information, and body data associated with said header.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |