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US5572476A
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Apparatus and method for determining the resistance of antifuses in an array
Assignee: Microsemi SoC Corp
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Filing: 1995-05-02
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Granted: 1996-11-05
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Expires: 2015-05-02
Abstract
Abstract An additional column (or row) track is provided in an antifuse based interconnect array containing circuit structures identical to the circuit structures in the remaining columns of the array, except that antifuse vias are filled with contact or via plugs. These plug antifuse substitutes are addressable in the same manner and by the same circuitry as the antifuses on the integrated circuit. The programmed antifuse is addressed, a test voltage is placed on the V pp input pin on the integrated circuit, and the current drawn by the antifuse is measured. The plug antifuse substitute is addressed, the test voltage is placed on the V pp input pin on the integrated circuit, and the current drawn by the plug antifuse substitute is measured. The resistance of the entire circuit path which includes the programmed antifuse is calculated using the test voltage and the measured antifuse current and the resistance of the entire circuit path which includes the plug antifuse substitute is calculated using the test voltage and the measured plug antifuse substitute current. The difference between the two resistance values is an accurate measure of the resistance of the programmed antifuse.
Inventors
- 👤 Abdelshafy A. Eltoukhy
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 12:45
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/02; G11C29/027; G11C17/00; G11C17/14; G11C17/18; G11C29/04; G11C29/50; G11C29/50008
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
219 words
An integrated circuit including a plurality of antifuses for selectively connecting together a plurality of interconnect conductors to provide programmed circuit paths for functional electronic circuits disposed on the integrated circuit, said integrated circuit further including: programming circuit means comprising at least one of said interconnect conductors having an interconnect conductor resistance, one of said plurality of antifuses, and at least one programming transistor having an on-resistance, said programming circuit means for forming a programming series circuit between a first voltage potential node in said integrated circuit and a second voltage potential node in said integrated circuit; reference circuit means comprising at least one reference conductor having a reference conductor resistance substantially equal to said interconnect conductor resistance, a via plug, and at least one reference transistor having an on-resistance substantially equal to the on resistance of said at least one programming transistor, said reference circuit means for forming a reference series circuit between said first and second voltage potential nodes; and programming circuit control means for selectively turning on said at least one programming transistor id response to signals identifying said one of said plurality of antifuses to create said programming series circuit and for selectively turning on said at least one reference transistor in response to signals identifying said via plug to create said reference series circuit.
Claim 2
Dependent Claim
219 words
An integrated circuit including a plurality of antifuses for selectively connecting together a plurality of interconnect conductors to provide programmed circuit paths for functional electronic circuits disposed on the integrated circuit, said integrated circuit further including: programming circuit means comprising at least one of said interconnect conductors having an interconnect conductor resistance, one of said plurality of antifuses, and at least one programming transistor having an on-resistance, said programming circuit means for forming a programming series circuit between a first voltage potential node in said integrated circuit and a second voltage potential node in said integrated circuit; reference circuit means comprising at least one reference conductor having a reference conductor resistance substantially equal to said interconnect conductor resistance, a via plug, and at least one reference transistor having an on-resistance substantially equal to the on resistance of said at least one programming transistor, said reference circuit means for forming a reference series circuit between said first and second voltage potential nodes; and programming circuit control means for selectively turning on said at least one programming transistor id response to signals identifying said one of said plurality of antifuses to create said programming series circuit and for selectively turning on said at least one reference transistor in response to signals identifying said via plug to create said reference series circuit.
Claim 3
Dependent Claim
109 words
An integrated circuit comprising: at least one circuit structure including functional circuitry, interconnect conductors, antifuses formed in vias for selectively connecting inputs and outputs of the functional circuitry to one another through at least one of said interconnect conductors, and at least one programming transistor for selectively applying a programming voltage potential across said antifuses; an antifuse resistance measurement structure electrically identical to said at least one circuit structure in which said antifuses are replaced by contact plugs in said visa; an input pin on said integrated circuit for applying a programming voltage potential to said integrated circuit; addressing circuitry for turning on selected ones of said programming transistors.
Claim 4
Dependent Claim
109 words
An integrated circuit comprising: at least one circuit structure including functional circuitry, interconnect conductors, antifuses formed in vias for selectively connecting inputs and outputs of the functional circuitry to one another through at least one of said interconnect conductors, and at least one programming transistor for selectively applying a programming voltage potential across said antifuses; an antifuse resistance measurement structure electrically identical to said at least one circuit structure in which said antifuses are replaced by contact plugs in said visa; an input pin on said integrated circuit for applying a programming voltage potential to said integrated circuit; addressing circuitry for turning on selected ones of said programming transistors.
Claim 5
Dependent Claim
208 words
An integrated circuit comprising: a first circuit node; a second circuit node; a first interconnect conductor; a second interconnect conductor; an antifuse connected between said first and second interconnect conductors; at least one first programming transistor connected between said first circuit node and said first interconnect conductor; at least one second programming transistor connected between said second circuit node and said second interconnect conductor; a first reference conductor, said first reference conductor having substantially the same resistance as said first interconnect conductor; a second reference conductor, said second reference conductor having substantially the same resistance as said second interconnect conductor; a via plug connected between said first and second reference conductors; at least one first reference transistor connected between said first circuit node and said first reference conductor, said at least one first reference transistor being substantially identical to said at least one first programming transistor; at least one second reference transistor connected between said second circuit node and said second reference conductor, said at least one second reference transistor being substantially identical to said at least one second programming transistor; addressing circuitry, connected to selectively turn on said at least one first and second programming transistors and to said at least one first and second reference transistors.
Claim 6
Dependent Claim
208 words
An integrated circuit comprising: a first circuit node; a second circuit node; a first interconnect conductor; a second interconnect conductor; an antifuse connected between said first and second interconnect conductors; at least one first programming transistor connected between said first circuit node and said first interconnect conductor; at least one second programming transistor connected between said second circuit node and said second interconnect conductor; a first reference conductor, said first reference conductor having substantially the same resistance as said first interconnect conductor; a second reference conductor, said second reference conductor having substantially the same resistance as said second interconnect conductor; a via plug connected between said first and second reference conductors; at least one first reference transistor connected between said first circuit node and said first reference conductor, said at least one first reference transistor being substantially identical to said at least one first programming transistor; at least one second reference transistor connected between said second circuit node and said second reference conductor, said at least one second reference transistor being substantially identical to said at least one second programming transistor; addressing circuitry, connected to selectively turn on said at least one first and second programming transistors and to said at least one first and second reference transistors.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |