US5572066A
Expired / Lapsed
US
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Lead-on-chip semiconductor device and method for its fabrication
Assignee: NXP USA Inc
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Filing: 1995-01-03
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Granted: 1996-11-05
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Expires: 2015-01-03
Abstract
Abstract A lead-on-chip (LOC) device (44) has a comb-shaped (32) or a cut-out (38) tape as the means of attachment for the leads (14) to the die surface. The LOC tape has cut-outs between the leads to minimize the amount of tape between the leads. The cut-outs are provided by either making the tape comb-shaped so that it has teeth and gaps between each tooth or by having oblong-shaped cut-outs in the tape corresponding in location the gaps between the leads. By minimizing the tape to die interface between the leads, the chance of voids forming between the leads is eliminated.
Inventors
- 👤 Sohrab Safai
- 👤 Michael C. Przano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 07:25
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/40; H10W70/411; H10W70/415; H10W72/00; H10W72/071; H10W72/073; H10W72/07351; H10W72/07352; H10W72/30; H10W72/321; H10W72/851; H10W72/853; H10W72/865; H10W90/00; H10W90/701; H10W90/731; H10W90/736; H10W90/751; H10W90/754; H10W90/756
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
105 words
A lead-on-chip (LOC) semiconductor device, comprising: a semiconductor die having a plurality of bonding pads on an active surface; a plurality of leads overlying the active surface of the semiconductor die; an electrically insulative adhesive tape between the semiconductor die and the plurality of leads to affix the plurality of leads to the active surface of the die, wherein the adhesive tape is disposed only in an area corresponding to the plurality of leads such that no adhesive tape is disposed between each of the plurality of leads; and a plurality of wire bonds connecting the plurality of leads to the plurality of bonding pads.
Claim 2
Dependent Claim
105 words
A lead-on-chip (LOC) semiconductor device, comprising: a semiconductor die having a plurality of bonding pads on an active surface; a plurality of leads overlying the active surface of the semiconductor die; an electrically insulative adhesive tape between the semiconductor die and the plurality of leads to affix the plurality of leads to the active surface of the die, wherein the adhesive tape is disposed only in an area corresponding to the plurality of leads such that no adhesive tape is disposed between each of the plurality of leads; and a plurality of wire bonds connecting the plurality of leads to the plurality of bonding pads.
Claim 3
Dependent Claim
17 words
The device of claim 1, wherein the semiconductor die is a memory device having peripheral bonding pads.
Claim 4
Dependent Claim
17 words
The device of claim 1, wherein the semiconductor die is a memory device having center bonding pads.
Claim 5
Dependent Claim
27 words
The device of claim 1, wherein the electrically insulative adhesive tape is composed of a material selected from a group consisting of a thermoset and a thermoplastic.
Claim 6
Dependent Claim
24 words
The device of claim 1, further comprising a package body encapsulating the active surface of the semiconductor die and the plurality of wire bonds.
Claim 7
Dependent Claim
106 words
A lead-on-chip (LOC) semiconductor device, comprising: a semiconductor die having a plurality of bonding pads on an active surface; a plurality of leads overlying the active surface of-the semiconductor die; an integral piece of electrically insulative adhesive tape having cut-outs between two continuous edges of the integral piece of tape, the integral piece of tape being disposed between the semiconductor die and the plurality of leads to affix the plurality of leads to-the active surface of the die, the cut-outs being located between each of the plurality of leads; and a plurality of wire bonds connecting the plurality of leads to the plurality of bonding pads.
Claim 8
Dependent Claim
106 words
A lead-on-chip (LOC) semiconductor device, comprising: a semiconductor die having a plurality of bonding pads on an active surface; a plurality of leads overlying the active surface of-the semiconductor die; an integral piece of electrically insulative adhesive tape having cut-outs between two continuous edges of the integral piece of tape, the integral piece of tape being disposed between the semiconductor die and the plurality of leads to affix the plurality of leads to-the active surface of the die, the cut-outs being located between each of the plurality of leads; and a plurality of wire bonds connecting the plurality of leads to the plurality of bonding pads.
Claim 9
Dependent Claim
17 words
The device of claim 6, wherein the semiconductor die is a memory device having peripheral bonding pads.
Claim 10
Dependent Claim
17 words
The device of claim 6, wherein the semiconductor die is a memory device having center bonding pads.
Claim 11
Dependent Claim
24 words
The device of claim 6, wherein the cut-outs in the integral piece of electrically insulative adhesive tape are characterized as having an oblong shape.
Claim 12
Dependent Claim
29 words
The device of claim 6, wherein the integral piece of electrically insulative adhesive tape is composed a material selected from a group consisting of a thermoset and a thermoplastic.
Claim 13
Dependent Claim
23 words
The device of claim 6, further comprising a package body encapsulating the active surface of-the semiconductor die and the plurality of wire bonds.
Claim 14
Independent Claim
133 words
A method for making a lead-on-chip (LOC) semiconductor device, comprising: providing a semiconductor die having a plurality of bonding pads on an active surface; providing an electrically insulative adhesive tape; attaching a plurality of leads to the active surface of the semiconductor die using the adhesive tape, wherein the adhesive tape is shaped to match the plurality of leads such that upon attaching the plurality of leads the active surface between adjacent leads remains exposed, without there being any adhesive tape exposed between adjacent leads; wire bonding the plurality of leads to the plurality of bonding pads to form a plurality of wire bonds electrically connecting the semiconductor die to the plurality of leads; and encapsulating the active surface of the semiconductor die and the plurality of wire bonds to protect the device.
Claim 15
Independent Claim
133 words
A method for making a lead-on-chip (LOC) semiconductor device, comprising: providing a semiconductor die having a plurality of bonding pads on an active surface; providing an electrically insulative adhesive tape; attaching a plurality of leads to the active surface of the semiconductor die using the adhesive tape, wherein the adhesive tape is shaped to match the plurality of leads such that upon attaching the plurality of leads the active surface between adjacent leads remains exposed, without there being any adhesive tape exposed between adjacent leads; wire bonding the plurality of leads to the plurality of bonding pads to form a plurality of wire bonds electrically connecting the semiconductor die to the plurality of leads; and encapsulating the active surface of the semiconductor die and the plurality of wire bonds to protect the device.
Claim 16
Dependent Claim
22 words
The method of claim 12, wherein the step of providing the semiconductor die comprises providing a memory device having peripheral bonding pads.
Claim 17
Dependent Claim
22 words
The method of claim 12, wherein the step of providing the semiconductor die comprises providing a memory device having center bonding pads.
References Cited (Backward Citations)
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| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |