Packaged semiconductor device having stress absorbing film

Claim 2

A packaged semiconductor device comprising: a semiconductor chip having a rectangularly shaped main surface in which an electronic device is formed; an electrically insulating film provided on said main surface of said semiconductor chip and having an electrically insulating base film, said insulating film being comb-shaped to include a bar portion extending in a first direction substantially parallel with a pair of parallel sides of said main surface of said chip and a plurality of substantially parallel finger portions extending from said bar portion in a second direction substantially perpendicular to said bar portion; a common inner lead bar formed on said bar portion of the insulating film; a plurality of leads each including an inner lead portion and an outer lead portion continuing from said inner lead portion, first parts of the inner lead portions of the leads respectively being formed on said finger portions of the insulating film; and a packaging material with which said semiconductor chip, said electrically insulating film, said common inner lead bar and said inner lead portions are sealed, said outer lead portions protruding from said packaging material, wherein said bar portion of the insulating film has an area large enough to provide a first insulating peripheral area portion not covered by said common inner lead bar, said first insulating peripheral area portion extending around said common inner lead bar, wherein each of said finger portions of the insulating film has another area large enough to provide a second insulating peripheral area portion not covered by said first part of its associated inner lead portion, said second insulating peripheral area portion extending around said first part of its associated inner lead portion, wherein each of said first and second insulating peripheral area portions have widths set to increase adherence of said comb-shaped insulating film to said packaging material and to said semiconductor chip to a degree which will prevent cracks in said packaging material adjacent to said common inner lead bar and said plurality of leads; and wherein said electrically insulating film has a thickness in a range from 80 μm to 200 μm, and said first and second peripheral area portions of said electrically insulating film not covered by said leads have a width measured from associated edges of said leads substantially in a range from 10 μm to 200 μm.

Claim 3

A packaged semiconductor device according to claim 1, in which said width of said first and second peripheral area portions of said electrically insulating film is substantially 100 μm.

Claim 4

A packaged semiconductor device according to claim 1, in which the thickness of said electrically insulating film is determined such that a capacitance between said chip and one of said leads is substantially. 1.2 pF or less.

Claim 5

A packaged semiconductor device according to claim 1, further comprising first and second adhesive layers provided on opposite first and second surfaces of said electrically insulating base film, respectively, said first adhesive layer being sandwiched between Said main surface of said chip and said electrically insulating base film and said second adhesive layer being sandwiched between said common inner lead bar and said electrically insulating base film and between said first parts of said inner lead portions and said base film.

Claim 6

A packaged semiconductor device comprising: a semiconductor chip having a rectangularly shaped main surface in which an electronic device is formed; a stress absorption film formed on said main surface of said semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of an ambient temperature; an electrically insulating film provided on said stress absorption film and having an electrically insulating base film, said insulating film being comb-shaped to include a bar portion extending in a first direction substantially parallel with a pair of parallel sides of said main surface of said chip and a plurality of substantially parallel finger portions extending from said bar portion in a second direction substantially perpendicular to said bar portion, said stress absorption film having a thermal expansion coefficient not smaller than that of said semiconductor chip and not larger than that of said electrically insulating film; a common inner lead bar formed on said bar portion of the insulating film; a plurality of leads each including an inner lead portion and an outer lead portion continuing from said inner lead portion, first parts of the inner lead portions of the leads being respectively formed on said finger portions of the insulating film; and a packaging material with which said semiconductor chip, said electrically insulating film, said common inner lead bar and said inner lead portions are sealed, said outer lead portions protruding from said packaging material, wherein said bar portion of the insulating film has an area large enough to provide a first insulating peripheral area portion not covered by said common inner lead bar, said first insulating peripheral area portion extending around said common inner lead bar, wherein each of said finger portions of the insulating film has another area large enough to provide a second insulating peripheral area portion not covered by said first part of its associated inner lead portion, said second insulating peripheral area portion extending around said first part of its associated inner lead portion, wherein each of said first and second insulating peripheral area portions have widths set to increase adherence of said comb-shaped insulating film to said packaging material and to said semiconductor chip to prevent cracks in said packaging material adjacent to said common inner lead bar and said plurality of leads, and wherein said electrically insulating film has a thickness in a range from 80 μm to 200 μm, and said first and second peripheral area portions of said electrically insulating film have width measured from associated edges of said leads in a range from 10 μm to 200 μm.

Claim 7

A packaged semiconductor device comprising: a semiconductor chip having a rectangularly shaped main surface in which an electronic device is formed; a stress absorption film formed on said main surface of said semiconductor chip for absorbing stress which may be produced in the packaged semiconductor device when subjected to variations of an ambient temperature; an electrically insulating film provided on said stress absorption film and having an electrically insulating base film, said insulating film being comb-shaped to include a bar portion extending in a first direction substantially parallel with a pair of parallel sides of said main surface of said chip and a plurality of substantially parallel finger portions extending from said bar portion in a second direction substantially perpendicular to said bar portion, said stress absorption film having a thermal expansion coefficient not smaller than that of said semiconductor chip and not larger than that of said electrically insulating film; a common inner lead bar formed on said bar portion of the insulating film; a plurality of leads each including an inner lead portion and an outer lead portion continuing from said inner lead portion, first parts of the inner lead portions of the leads being respectively formed on said finger portions of the insulating film; and a packaging material with which said semiconductor chip, said electrically insulating film, said common inner lead bar and said inner lead portions are sealed, said outer lead portions protruding from said packaging material, wherein said bar portion of the insulating film has an area large enough to provide a first insulating peripheral area portion not covered by said common inner lead bar, said first insulating peripheral area portion extending around said common inner lead bar, wherein each of said finger portions of the insulating film has another area large enough to provide a second insulating peripheral area portion not covered by said first part of its associated inner lead portion, said second insulating peripheral area portion extending around said first part of its associated inner lead portion, wherein each of said first and second insulating peripheral area portions have widths set to increase adherence of said comb-shaped insulating film to said packaging material and to said semiconductor chip to prevent cracks in said packaging material adjacent to said common inner lead bar and said plurality of leads, and wherein said electrically insulating film has a thickness in a range from 80 μm to 200 μm, and said first and second peripheral area portions of said electrically insulating film have width measured from associated edges of said leads in a range from 10 μm to 200 μm.

Claim 8

A packaged semiconductor device according to claim 5, in which both of said stress absorption film and said electrically insulating film are made of a polyimide resin.

Claim 9

A packaged semiconductor device according to claim 5, in which said stress absorption film serves to produce compressive stress to said chip.

Claim 10

A packaged semiconductor device according to claim 5, in which said width of said first and second peripheral area portions of said electrically insulating film is substantially 100 μm.

Claim 11

A packaged semiconductor device according to claim 5, further comprising first and second adhesive layers provided on opposite first and second surfaces of said electrically insulating base film, respectively, said first adhesive layer being sandwiched between said stress absorption film and said electrically insulating base film and said second adhesive layer being sandwiched between said common inner lead bar and said electrically insulating base film and between said first parts of said inner lead portions and said base film.