Patent US5571744A successfully refreshed from Google Patents.
US5571744A
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US
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Defect free CMOS process
Assignee: National Semiconductor Corp
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Filing: 1993-08-27
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Granted: 1996-11-05
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Expires: 2013-08-27
Abstract
Abstract A method for manufacturing CMOS semiconductor devices wherein damage to the active regions of the devices due to the direct implantation of impurities is suppressed. A material is selectively deposited on a semiconductor substrate, the material having a characteristic such that formation of the material occurs on some substances such as silicon and polysilicon, and formation of the material is suppressed on other substances such as silicon dioxide and silicon nitride. Impurities are introduced into the material rather than into the substrate. The impurities are then diffused into the active regions by standard processes such as rapid thermal anneal (RTA) or furnace anneal. The material generally contains germanium, and usually is a polycrystalline silicon-germanium alloy. The diffusion depth of the impurities may be controlled with great precision by manipulating several parameters. The parameters include the thickness of the material, the energy of the impurity implants, the density of the impurity implants, and the concentration of germanium in the material.
Inventors
- 👤 Esin K. Demirlioglu
- 👤 Sheldon Aronowitz
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 23:25
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10P; H10P32/00; H10P32/10; H10P32/14; H10D62/00; H10D62/80; H10D62/83; H10D62/832; H10D62/834; H10D64/00; H10D64/01; H10D64/017; H10D64/20; H10D64/23; H10D64/251; H10D64/258; H10D64/259; H10D64/60; H10D64/62; H10D64/66; H10D64/661; H10D64/662; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0165; H10D84/0172; H10D84/0174; H10D84/02; H10D84/03; H10D84/038; H10P32/1408; H10P32/17; H10P32/171; H10D30/0212
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
237 words
A method for manufacturing a CMOS device having a substrate, the method using a self-aligned process wherein damage to active regions of the device due to direct implantation of impurities is suppressed, the method comprising the steps of: forming wells in the device substrate; isolating the active regions of the device; selectively forming a first buffer material on the active regions, the first buffer material comprising germanium; introducing first impurities into the first buffer material; diffusing the first impurities into the active regions; selectively removing the first buffer material; forming a gate dielectric layer on the device; depositing a polysilicon layer on the gate dielectric layer; depositing a first suppressant layer on the polysilicon layer; defining gates on the active regions, the gates comprising portions of the gate dielectric layer, the polysilicon layer, and the first suppressant layer; depositing a second suppressant layer on the device; etching the second suppressant layer to form dielectric spacers on the sides of the gates; removing the first suppressant layer from the polysilicon layer of each gate; selectively depositing a second buffer material on the polysilicon layer of each gate and any exposed areas of the active regions, the second buffer material comprising germanium; introducing second impurities into the second buffer material; diffusing the second impurities into the active regions to form source and drain regions, and into the polysilicon layer of each gate; and forming contacts on the second material.
Claim 2
Independent Claim
237 words
A method for manufacturing a CMOS device having a substrate, the method using a self-aligned process wherein damage to active regions of the device due to direct implantation of impurities is suppressed, the method comprising the steps of: forming wells in the device substrate; isolating the active regions of the device; selectively forming a first buffer material on the active regions, the first buffer material comprising germanium; introducing first impurities into the first buffer material; diffusing the first impurities into the active regions; selectively removing the first buffer material; forming a gate dielectric layer on the device; depositing a polysilicon layer on the gate dielectric layer; depositing a first suppressant layer on the polysilicon layer; defining gates on the active regions, the gates comprising portions of the gate dielectric layer, the polysilicon layer, and the first suppressant layer; depositing a second suppressant layer on the device; etching the second suppressant layer to form dielectric spacers on the sides of the gates; removing the first suppressant layer from the polysilicon layer of each gate; selectively depositing a second buffer material on the polysilicon layer of each gate and any exposed areas of the active regions, the second buffer material comprising germanium; introducing second impurities into the second buffer material; diffusing the second impurities into the active regions to form source and drain regions, and into the polysilicon layer of each gate; and forming contacts on the second material.
Claim 3
Dependent Claim
15 words
The method of claim 1 wherein the first and second buffer materials comprise silicon-germanium alloys.
Claim 4
Dependent Claim
21 words
The method of claim 1 wherein the step of diffusing the first and second impurities comprises performing a furnace anneal process.
Claim 5
Dependent Claim
22 words
The method of claim 1 wherein the step of diffusing the first and second impurities comprises performing a rapid thermal anneal process.
Claim 6
Dependent Claim
15 words
The method of claim 1 wherein the first and second suppressant layers comprise dielectric materials.
Claim 7
Dependent Claim
13 words
The method of claim 6 wherein the first suppressant layer comprises an oxide.
Claim 8
Dependent Claim
13 words
The method of claim 1 wherein the second suppressant layer comprises an oxide.
Claim 9
Dependent Claim
13 words
The method of claim 1 wherein the first suppressant layer comprises a nitride.
Claim 10
Dependent Claim
13 words
The method of claim 1 wherein the second suppressant layer comprises a nitride.
Claim 11
Dependent Claim
72 words
The method of claim 1 wherein the diffusing steps result in the first impurities and the second impurities diffusing to diffusion depths, the diffusion depths being controlled by a plurality of parameters, the parameters comprising thickness of the first and second buffer materials, energy of the first impurities and the second impurities, density of the first impurities and the second impurities, and concentration of germanium in the first and second buffer materials.
Claim 12
Independent Claim
404 words
A method for manufacturing a CMOS device having a substrate, the method using a self-aligned process wherein damage to active regions of the device due to direct implantation of impurities is suppressed, the method comprising the steps of: forming p-type regions and n-type wells in the substrate of the device; isolating the active regions of the device; forming a first silicon-germanium alloy on the active regions of the device; forming a first mask over the active regions so as to shield portions of the first silicon-germanium alloy overlying the n-type wells from a subsequent implant step; introducing first n-type dopant implants into the first silicon-germanium alloy; removing the first mask; forming a second mask over the active regions so as to shield portions of the first silicon-germanium alloy overlying the p-type regions from a subsequent implant step; introducing first p-type dopant implants into the first silicon-germanium alloy; removing the second mask; diffusing the first n-type dopant implants and the first p-type dopant implants into the active regions of the device; removing the first silicon-germanium alloy; forming a gate dielectric layer on the device; depositing a polysilicon layer on the gate dielectric layer; depositing a nitride layer on the polysilicon layer; defining gates on the active regions, the gates comprising portions of the gate dielectric layer, the polysilicon layer, and the nitride layer; depositing a spacer dielectric layer on the device; etching the spacer dielectric layer to form dielectric spacers on the sides of the gates; removing the nitride layer on the polysilicon layer of each of said gates; depositing a second silicon-germanium alloy on the polysilicon layer of each of said gates and on any exposed areas of the active regions; forming a third mask over the active regions so as to shield portions of the second silicon-germanium alloy overlying the n-type wells from a subsequent implant step; introducing second p-type dopant implants into the second silicon-germanium alloy; removing the third mask; forming a fourth mask over the active regions so as to shield portions of the second silicon-germanium alloy overlying the p-type regions from a subsequent implant step; introducing second n-type dopant implants into the second silicon-germanium alloy; removing the fourth mask; diffusing the second p-type dopant implants and the second n-type dopant implants into the active regions to form source and drain regions, and into the polysilicon layer of each of said gates; and forming silicide contacts on the second silicon-germanium alloy.
Claim 13
Independent Claim
404 words
A method for manufacturing a CMOS device having a substrate, the method using a self-aligned process wherein damage to active regions of the device due to direct implantation of impurities is suppressed, the method comprising the steps of: forming p-type regions and n-type wells in the substrate of the device; isolating the active regions of the device; forming a first silicon-germanium alloy on the active regions of the device; forming a first mask over the active regions so as to shield portions of the first silicon-germanium alloy overlying the n-type wells from a subsequent implant step; introducing first n-type dopant implants into the first silicon-germanium alloy; removing the first mask; forming a second mask over the active regions so as to shield portions of the first silicon-germanium alloy overlying the p-type regions from a subsequent implant step; introducing first p-type dopant implants into the first silicon-germanium alloy; removing the second mask; diffusing the first n-type dopant implants and the first p-type dopant implants into the active regions of the device; removing the first silicon-germanium alloy; forming a gate dielectric layer on the device; depositing a polysilicon layer on the gate dielectric layer; depositing a nitride layer on the polysilicon layer; defining gates on the active regions, the gates comprising portions of the gate dielectric layer, the polysilicon layer, and the nitride layer; depositing a spacer dielectric layer on the device; etching the spacer dielectric layer to form dielectric spacers on the sides of the gates; removing the nitride layer on the polysilicon layer of each of said gates; depositing a second silicon-germanium alloy on the polysilicon layer of each of said gates and on any exposed areas of the active regions; forming a third mask over the active regions so as to shield portions of the second silicon-germanium alloy overlying the n-type wells from a subsequent implant step; introducing second p-type dopant implants into the second silicon-germanium alloy; removing the third mask; forming a fourth mask over the active regions so as to shield portions of the second silicon-germanium alloy overlying the p-type regions from a subsequent implant step; introducing second n-type dopant implants into the second silicon-germanium alloy; removing the fourth mask; diffusing the second p-type dopant implants and the second n-type dopant implants into the active regions to form source and drain regions, and into the polysilicon layer of each of said gates; and forming silicide contacts on the second silicon-germanium alloy.
Claim 14
Dependent Claim
19 words
The method of claim 11 wherein the diffusing of the dopant implants is accomplished using a furnace anneal process.
Claim 15
Dependent Claim
20 words
The method of claim 11 wherein the diffusing of the dopant implants is accomplished using a rapid thermal anneal process.
Claim 16
Dependent Claim
55 words
The method of claim 11 wherein the diffusing steps result in the dopant implants diffusing to a diffusion depth, the diffusion depth being controlled by a plurality of parameters, the parameters comprising thickness of the silicon-germanium alloys, energy of the dopant implants, density of the dopant implants, and concentration of germanium in the silicon-germanium alloys.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-11-05 | 2000-05-06 | 2000-11-05 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-11-05 | 2004-05-06 | 2004-11-05 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-11-05 | 2008-05-06 | 2008-11-05 | $7700.00 | Window Closed / Lapsed |