Patent US5570381A successfully refreshed from Google Patents.
US5570381A
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Synchronous DRAM tester
Assignee: Chartoleaux KG LLC
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Filing: 1995-04-28
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Granted: 1996-10-29
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Expires: 2015-04-28
Abstract
Abstract A method of testing synchronous dynamic random access memories (SDRAMs) having a pair of memory banks, comprised of writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring the data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading the second of the pair of memory banks at the first clock speed to the tester.
Inventors
- 👤 Paul Schofield
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 19:37
CPC Classifications
G; G11; G11C; G11C29/00; G11C29/04; G11C29/08; G11C29/12; G11C29/12015; G11C29/14; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
95 words
A method of testing an synchronous dynamic random access memory (SDRAM) having a pair of memory banks, comprising writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring said data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading data from the second of the pair of memory banks at the first clock speed to the tester.
Claim 2
Independent Claim
95 words
A method of testing an synchronous dynamic random access memory (SDRAM) having a pair of memory banks, comprising writing data into a first of the pair of memory banks at a first clock speed that can be used by a tester, transferring said data at a second clock speed much higher than the first clock speed from the first of the pair of memory banks to a second of the pair of memory banks, and then reading data from the second of the pair of memory banks at the first clock speed to the tester.
Claim 3
Dependent Claim
54 words
A method as defined in claim 1 in which the data written into the first of the pair of memory banks is a test pattern, and said step of transferring said data is done at a clock speed which is higher than a clock speed used to read the test pattern to the tester.
Claim 4
Dependent Claim
21 words
A method as defined in claim 2 in which said higher clock speed is a design rated speed of the SDRAM.
Claim 5
Dependent Claim
87 words
A method as defined in claim 2 including input bus and an output bus both accessible by said pair of memory banks, and a bidirectional bus, in which the output bus is coupled to the data bus via plural output latches, and the input bus is coupled to the data bus via plural input latches, the transferring step including enabling both the input and output latches simultaneously while the first memory bank is in a read mode and the second memory bank is in a write mode.
Claim 6
Dependent Claim
49 words
A method as defined in claim 4 in which the transferring step is conducted by placing both the first and second memory banks in a full page burst length mode whereby the entire contents of the first memory bank is transferred to the second memory bank in one operation.
Claim 7
Dependent Claim
88 words
A method as defined in claim 1 including an input bus and an output bus both accessible by said pair of memory banks, and a bidirectional bus, in which the output bus is coupled to the data bus via plural output latches, and the input bus is coupled to the data bus via plural input latches, the transferring step including enabling both the input and output latches simultaneously while the first memory bank is in a read mode and the second memory bank is in a write mode.
Claim 8
Dependent Claim
49 words
A method as defined in claim 1 in which the transferring step is conducted by placing both the first and second memory banks in a full page burst length mode whereby the entire contents of the first memory bank is transferred to the second memory bank in one operation.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-29 | 2000-04-29 | 2000-10-29 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-29 | 2004-04-29 | 2004-10-29 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-29 | 2008-04-29 | 2008-10-29 | $7700.00 | Window Closed / Lapsed |