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US5570060A Expired / Lapsed US ⏱️ 0.0 years remaining

Circuit for limiting the current in a power transistor

Assignee: STMicroelectronics lnc USA
•
Filing: 1995-03-28
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Granted: 1996-10-29
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Expires: 2015-03-28
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Abstract

Abstract A current limiting circuit used with voltage regulators or other similar circuits is disclosed. The current limiting circuit uses two transistors, configured as a differential pair, combined with a fixed current source to limit the current available to a pass transistor of the voltage regulator.

Inventors

  • 👤 William E. Edwards

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-09 19:15
CPC Classifications
G; G05; G05F; G05F3/00; G05F3/02; G05F3/08; G05F3/10; G05F3/16; G05F3/20; G05F3/26; G05F3/267; G05F1/00; G05F1/10; G05F1/46; G05F1/56; G05F1/575

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 212 words
A voltage regulator for providing a regulated voltage on an output responsive to a voltage (V trk ), said voltage regulator comprising: an error amplifier having a first input for receiving the voltage (V trk ), having an second input coupled to the output of the voltage regulator, and having an output; a pass transistor having a current path between a voltage source and the output of the voltage regulator, and having a control element, a first transistor having a control element coupled to the output of the error amplifier, and having a current path with a first end and a second end; a second transistor having a control element for receiving a bias voltage and having a current path with a first end coupled to the source voltage and a second end, wherein the current path of the first transistor is in parallel with the current path of the second transistor; a fixed current source coupled in series with the current path of the first transistor and the current path of the second transistor; and an output transistor having a current path coupled in series the current path of the first transistor and having a control element coupled to its current path and to the control element of the pass element.
Claim 2
Dependent Claim 212 words
A voltage regulator for providing a regulated voltage on an output responsive to a voltage (V trk ), said voltage regulator comprising: an error amplifier having a first input for receiving the voltage (V trk ), having an second input coupled to the output of the voltage regulator, and having an output; a pass transistor having a current path between a voltage source and the output of the voltage regulator, and having a control element, a first transistor having a control element coupled to the output of the error amplifier, and having a current path with a first end and a second end; a second transistor having a control element for receiving a bias voltage and having a current path with a first end coupled to the source voltage and a second end, wherein the current path of the first transistor is in parallel with the current path of the second transistor; a fixed current source coupled in series with the current path of the first transistor and the current path of the second transistor; and an output transistor having a current path coupled in series the current path of the first transistor and having a control element coupled to its current path and to the control element of the pass element.
Claim 3
Dependent Claim 24 words
The current limiting circuit of claim 1 wherein the first and second transistor comprise bipolar transistors and the output transistor is a MOSFET transistor.
Claim 4
Dependent Claim 17 words
The current limiting circuit of claim 2 wherein the first and second transistors are NPN bipolar transistors.
Claim 5
Dependent Claim 16 words
The current limiting circuit of claim 2 wherein the output transistor is a p-channel MOSFET transistor.
Claim 6
Dependent Claim 16 words
The current limiting circuit of claim 1 wherein the fixed current source comprises a current mirror.

References Cited (Backward Citations)

US3718864A Cited
US5159260A Cited
US4327320A Cited
US4438349A Cited
US4338646A Cited
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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-10-29 2000-04-29 2000-10-29 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-10-29 2004-04-29 2004-10-29 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-10-29 2008-04-29 2008-10-29 $7700.00 Window Closed / Lapsed

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