Multiple instruction set mapping

Claim 1

Apparatus for processing data, said apparatus comprising: (i) a processor core responsive to a plurality of core control signals; (ii) decoding means for decoding P bits of an X-bit program instruction word of a first instruction set to generate said core control signals; (iii) an instruction pipeline through which instruction program words are passed to said decoding means; and (iv) first mapping means responsive to a Y-bit program instruction word of a second instruction set passing along said instruction pipeline for mapping Q bits of said Y-bit program instruction word to said P bits of a corresponding X-bit program instruction word for decoding by said decoding means, wherein (v) Y is less than X, P is less than X and said second instruction set is a subset of said first instruction set; and (vi) instruction program words pass through said instruction pipeline over a plurality of processing cycles, one of said processing cycles being a decode cycle, said decoding means being operative to produce said core control signals by the end of said decode cycle and said first mapping means being operative to produce said P bits of said corresponding X-bit program instruction word during a first portion of said decode cycle to enable said decoding means still to produce said core control signals by the end of said decode cycle.

Claim 14

A method of processing data, said method comprising the steps of: (i) providing a processor core responsive to a plurality of core control signals; (ii) decoding P bits of an X-bit program instruction word of a first instruction set with a decoding means to generate core control signals for controlling a processor core; (iii) passing instruction program words through an instruction pipeline to said decoding means; and (iv) mapping Q bits of a Y-bit program instruction word of a second instruction set passing along said instruction pipeline to said P bits of a corresponding X-bit program instruction word for decoding by said decoding means, wherein (v) Y is less than X, P is less than X and said second instruction set is a subset of said first instruction set; and (vi) instruction program words pass through said instruction pipeline over a plurality of processing cycles, one of said processing cycles being a decode cycle, said decoding operating to produce said core control signals by the end of said decode cycle, and said mapping operating to produce said P bits of said corresponding X-bit program instruction word during a first portion of said decode cycle to enable production of said core control signals by the end of said decode cycle.

Claim 15

A method of processing data, said method comprising the steps of: (i) providing a processor core responsive to a plurality of core control signals; (ii) decoding P bits of an X-bit program instruction word of a first instruction set with a decoding means to generate core control signals for controlling a processor core; (iii) passing instruction program words through an instruction pipeline to said decoding means; and (iv) mapping Q bits of a Y-bit program instruction word of a second instruction set passing along said instruction pipeline to said P bits of a corresponding X-bit program instruction word for decoding by said decoding means, wherein (v) Y is less than X, P is less than X and said second instruction set is a subset of said first instruction set; and (vi) instruction program words pass through said instruction pipeline over a plurality of processing cycles, one of said processing cycles being a decode cycle, said decoding operating to produce said core control signals by the end of said decode cycle, and said mapping operating to produce said P bits of said corresponding X-bit program instruction word during a first portion of said decode cycle to enable production of said core control signals by the end of said decode cycle.