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US5568424A Expired / Lapsed US ⏱️ 0.0 years remaining

Programmable power generation circuit for flash EEPROM memory systems

Assignee: EMS Technologies LLC
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Filing: 1995-06-07
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Granted: 1996-10-22
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Expires: 2015-06-07
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Abstract

Abstract An flash EEPROM system functioning as a mass storage medium for a host computer includes a controller and at least one flash EEPROM memory module. The flash EEPROM memory module includes at least one flash EEPROM chip having an on-chip programmable power generation circuit including a high voltage generator circuit capable of generating a high voltage Vpp from a logic level voltage Vdd provided to the chip, a serial protocol logic circuit, a data latch, a data bus, a register address decoder, and a multi-voltage generator/regulator. The multi-voltage generator/regulator includes a plurality of registers and provides the programming, reading, and erasing voltages required for proper operation of the flash EEPROM system from digital values stored in the plurality of registers by the controller. The high voltage generator circuit includes both high current and low current charge pump circuits for generating the high voltage Vpp. The high current charge pump circuit is connected to relatively large off-chip charge storage devices, and the low current charge pump circuit is connected to relatively small on-chip charge storage devices. The controller may activate one or the other of the high or low current charge pump circuits through control signals connected to enabling circuitry respectively connected to the high and low current charge pump circuits. Alternatively, the controller may deactivate both the high and low current charge pump circuits and cause the high voltage Vpp to be provided from other circuitry on another flash EEPROM chip in the flash EEPROM module.

Inventors

  • 👤 Raul-Adrian Cernea
  • 👤 Douglas J. Lee
  • 👤 Mehrdad Mofidi
  • 👤 Sanjay Mehrotra

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-01 04:18
CPC Classifications
G; G11; G11C; G11C16/00; G11C16/02; G11C16/06; G11C16/30; G11C16/10; G11C16/14; G11C16/16

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 89 words
A flash EEPROM system comprising: at least one integrated circuit chip having an array of flash EEPROM cells; a controller for controlling operations of said at least one integrated circuit chip; and a programmable power source resident on said at least one integrated circuit chip, for supplying a plurality of voltages to selected ones of said array of flash EEPROM cells of said at least one integrated circuit chip, wherein said plurality of voltages are programmed by said controller in response to predefined parameters of the flash EEPROM system.
Claim 2
Dependent Claim 89 words
A flash EEPROM system comprising: at least one integrated circuit chip having an array of flash EEPROM cells; a controller for controlling operations of said at least one integrated circuit chip; and a programmable power source resident on said at least one integrated circuit chip, for supplying a plurality of voltages to selected ones of said array of flash EEPROM cells of said at least one integrated circuit chip, wherein said plurality of voltages are programmed by said controller in response to predefined parameters of the flash EEPROM system.
Claim 3
Dependent Claim 66 words
The flash EEPROM system as recited in claim 1, wherein said programmable power source comprises: a plurality of registers respectively storing information indicative of said plurality of voltages programmed by said controller; and a plurality of digital-to-analog converters individually coupled to at least one of said plurality of registers to provide an analog output voltage proportional to the information stored in said at least one register.
Claim 4
Dependent Claim 61 words
The flash EEPROM system as recited in claim 2, wherein said programmable power source further comprises a plurality of amplifiers, each amplifier coupled to a respective one of said plurality of digital-to-analog converters and having a regulated voltage output indicative of the information stored in the at least one register coupled to said respective one of said plurality of digital-to-analog converters.
Claim 5
Dependent Claim 46 words
The flash EEPROM system as recited in claim 3, wherein said plurality of registers of said programmable power source include a bit line voltage register for storing information indicative of a bit line voltage suitable for programming selected ones of said array of flash EEPROM cells.
Claim 6
Dependent Claim 75 words
The flash EEPROM system as recited in claim 3, wherein said plurality of registers of said programmable power source include a first control gate voltage register for storing information indicative of a word line voltage suitable for programming selected ones of said array of flash EEPROM cells, and a second control gate voltage register for storing information indicative of a word line voltage suitable for reading selected ones of said array of flash EEPROM cells.
Claim 7
Dependent Claim 64 words
The flash EEPROM system as recited in claim 5, wherein said plurality of registers of said programmable power source includes an erase gate voltage register for storing information indicative of a suitable erase gate voltage to be applied to the erase gates of selected ones of said array of flash EEPROM cells while reading said selected ones of said array of flash EEPROM cells.
Claim 8
Dependent Claim 77 words
The flash EEPROM system as recited in claim 6, wherein said programmable power source further comprises a charge pump circuit responsive to an erase mode signal and an output of the digital-to-analog converter coupled to said erase gate voltage register, for generating a suitable erase gate voltage to be applied to the erase gates of selected ones of said array of flash EEPROM cells while concurrently erasing said selected ones of said array of flash EEPROM cells.

References Cited (Backward Citations)

US4970692A Cited
US5172338A Cited
US5418752A Cited
US5172338B1 Cited
US5430859A Cited
US5267218A Cited
US5426391A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-10-22 2000-04-22 2000-10-22 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-10-22 2004-04-22 2004-10-22 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-10-22 2008-04-22 2008-10-22 $7700.00 Window Closed / Lapsed

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