Method and system for the design verification of logic units and use in different environments

Claim 1

A method for the logic design verification of a logic unit wherein the logic unit includes at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units include a set of test operations which are carried into execution by the logic unit, said method comprising the steps of: selecting, at said at least one test units a test operation from the set of test operations included therein, wherein said selection of said test operation at each of said at least one test units is performed pseudo-randomly and wherein said selection of said test operation at one of said at least one test units is independent from the selection of a test operation at the others of said at least one test units; and determining the starting times of the test operation for each of said at least one test units, wherein said determination of the starting times of the test operation for each of the at least one test units is performed pseudo-randomly and wherein said determination of a starting time at one of the at least one test units is independent from the determination of the starting times of the test operation at the others of said at least one test units; and providing said selected test operation to said logic unit at said determined start times via said at least one interface means to determine if there are any logical failures associated with the logic unit so as to verify the logical design of the logic unit; wherein the step of selecting the test operations and the step of determining the starting times of the test operations at each of said at least one test units are executed independently of each other.

Claim 2

A method for the logic design verification of a logic unit wherein the logic unit includes at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units include a set of test operations which are carried into execution by the logic unit, said method comprising the steps of: selecting, at said at least one test units a test operation from the set of test operations included therein, wherein said selection of said test operation at each of said at least one test units is performed pseudo-randomly and wherein said selection of said test operation at one of said at least one test units is independent from the selection of a test operation at the others of said at least one test units; and determining the starting times of the test operation for each of said at least one test units, wherein said determination of the starting times of the test operation for each of the at least one test units is performed pseudo-randomly and wherein said determination of a starting time at one of the at least one test units is independent from the determination of the starting times of the test operation at the others of said at least one test units; and providing said selected test operation to said logic unit at said determined start times via said at least one interface means to determine if there are any logical failures associated with the logic unit so as to verify the logical design of the logic unit; wherein the step of selecting the test operations and the step of determining the starting times of the test operations at each of said at least one test units are executed independently of each other.

Claim 6

A method for the design verification of a logic unit wherein the logic unit includes at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units include a set of test operations which are carried into execution by the logic unit, said method comprising the steps of: selecting the test operations; determining the starting times of the test operations; and providing the selected test operations to the logic unit at said determined starting times via the at least one interface means to verify the logical design of the logic unit; wherein the selecting of the test operations and determining the starting times of the test operations are executed pseudo-randomly and independently of each other, and wherein each of the test units comprise an interface protocol level and a level for the selection of test operations, and wherein the selection of the test operations is carried out by an operation select pointer, which is supplied with a pseudo-random number generated by a modulo operation based on an initial pseudo-random number and a maximum number of test operations.

Claim 7

A method for the design verification of a logic unit wherein the logic unit includes at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units include a set of test operations which are carried into execution by the logic unit, said method comprising the steps of: selecting the test operations; determining the starting times of the test operations; and providing the selected test operations to the logic unit at said determined starting times via the at least one interface means to verify the logical design of the logic unit; wherein the selecting of the test operations and determining the starting times of the test operations are executed pseudo-randomly and independently of each other, and wherein each of the test units comprise an interface protocol level and a level for the selection of test operations, and wherein the selection of the test operations is carried out by an operation select pointer, which is supplied with a pseudo-random number generated by a modulo operation based on an initial pseudo-random number and a maximum number of test operations.

Claim 13

A system for the logic design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: a set of test operations to be carried into execution by the logic unit; means for a pseudo-random selection of a test operation from said included set of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations applied to said logic unit, said comparison means permitting the determination of logical failures associated with said logic unit so as to verify the logical design of said logic unit; trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; and wherein said means for pseudo-random selection of the test operations and said trigger means for pseudo-randomly determining the starting times of each of the test operations operate independently of each other.

Claim 14

A system for the logic design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: a set of test operations to be carried into execution by the logic unit; means for a pseudo-random selection of a test operation from said included set of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations applied to said logic unit, said comparison means permitting the determination of logical failures associated with said logic unit so as to verify the logical design of said logic unit; trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; and wherein said means for pseudo-random selection of the test operations and said trigger means for pseudo-randomly determining the starting times of each of the test operations operate independently of each other.

Claim 16

A system for the design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: means for a pseudo-random selection of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations performed on said logic unit, said comparison means permitting the determination of logical failures associated with said logic unit so as to verify the logical design of said logic unit; and trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; wherein each test unit exhibits a level for the bus protocol, a level for the selection of test operations which are applied to the logic unit, and a level for the data generation and the data comparison, and wherein the trigger means are connected with the operation select level of each test unit by two data lines, a first line for providing a START signal from the trigger means to the operation select level of each test unit, and a second line for providing a DONE signal from the operation select level of each data unit to the trigger means.

Claim 17

A system for the design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: means for a pseudo-random selection of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations performed on said logic unit, said comparison means permitting the determination of logical failures associated with said logic unit so as to verify the logical design of said logic unit; and trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; wherein each test unit exhibits a level for the bus protocol, a level for the selection of test operations which are applied to the logic unit, and a level for the data generation and the data comparison, and wherein the trigger means are connected with the operation select level of each test unit by two data lines, a first line for providing a START signal from the trigger means to the operation select level of each test unit, and a second line for providing a DONE signal from the operation select level of each data unit to the trigger means.

Claim 19

A system for the design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: means for a pseudo-random selection of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations performed on said logic unit, said comparison means permitting the determination of logical failures associated with the logic unit so as to verify the logical design of said logic unit; and trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; wherein each test unit exhibits a level for the bus protocol, a level for the selection of test operations which are applied to the logic unit, and a level for the data generation and the data comparison, and wherein the operation select level has at least one pseudo-random pattern means comprising a pseudo-random pattern generator, a register for the maximum number of operations, a modulo operation device, an operation select pointer and a storage means which keeps a collection of the available operations.

Claim 20

A system for the design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: means for a pseudo-random selection of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations performed on said logic unit, said comparison means permitting the determination of logical failures associated with the logic unit so as to verify the logical design of said logic unit; and trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; wherein each test unit exhibits a level for the bus protocol, a level for the selection of test operations which are applied to the logic unit, and a level for the data generation and the data comparison, and wherein the operation select level has at least one pseudo-random pattern means comprising a pseudo-random pattern generator, a register for the maximum number of operations, a modulo operation device, an operation select pointer and a storage means which keeps a collection of the available operations.

Claim 21

A system for the design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: means for a pseudo-random selection of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations performed on said logic unit, said comparison means permitting the determination of logical failures associated with the logic unit so as to verify the logical design of said logic unit; and trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; and wherein the trigger means has at least one pseudo-random pattern means for each test unit, which comprises: a pseudo-random pattern generator generating pseudo-random numbers, a register for the maximum number of waiting cycles until the starting times of the operations, a modulo operation device which executes a modulo operation by use of the content of the pseudo-random pattern generator and the maximum number of waiting cycles, a reverse counter using the result of the modulo operation as the start number, and a start signal generator which effects the beginning of a test operation at a zero count of the reverse counter.

Claim 22

A system for the design verification of a logic unit, which has at least one interface means and at least one bus means for external communication and operation means for operating a bus protocol, with at least one test unit, which is connected to the logic unit via the at least one interface means, and wherein each test unit comprises: means for a pseudo-random selection of test operations, which are applied to the logic unit; means for data generation and data comparison, which are used for comparing the generated data with the data obtained from the test operations performed on said logic unit, said comparison means permitting the determination of logical failures associated with the logic unit so as to verify the logical design of said logic unit; and trigger means being connected with each of the test units, the trigger means being used for pseudo-randomly determining the starting times of each of the test operations, respectively; and wherein the trigger means has at least one pseudo-random pattern means for each test unit, which comprises: a pseudo-random pattern generator generating pseudo-random numbers, a register for the maximum number of waiting cycles until the starting times of the operations, a modulo operation device which executes a modulo operation by use of the content of the pseudo-random pattern generator and the maximum number of waiting cycles, a reverse counter using the result of the modulo operation as the start number, and a start signal generator which effects the beginning of a test operation at a zero count of the reverse counter.

Claim 23

A system for the logic design verification of a logic unit where the logic unit comprises at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units comprise a set of test operations which are carried into execution by the logic unit, and wherein each of said test units further comprises: means for pseudo-randomly selecting test operations from the set of test operations included therein to be applied to the logic unit, wherein the selection means enable the selection of the test operations at one of said at least one test units to be executed independently from the selection of the test operations at the others of said at least one test units; means for pseudo-randomly determining the starting times of the test operations, wherein the determination means enable the determination of the starting times of the test operations at one of said at least one test units to be executed independently from the determination of the starting times of the test operations at the others of said at least one test units; and means for providing said selected test operations to said logic unit at said determined start times via said at least one interface means to determine whether there are any logical failures associated with the logic unit so as to verify the logical design of the logic unit; wherein both the selection of test operations and the determination of their start times are executed pseudo-randomly and independently of each other at each of the at least one test units.

Claim 24

A system for the logic design verification of a logic unit where the logic unit comprises at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units comprise a set of test operations which are carried into execution by the logic unit, and wherein each of said test units further comprises: means for pseudo-randomly selecting test operations from the set of test operations included therein to be applied to the logic unit, wherein the selection means enable the selection of the test operations at one of said at least one test units to be executed independently from the selection of the test operations at the others of said at least one test units; means for pseudo-randomly determining the starting times of the test operations, wherein the determination means enable the determination of the starting times of the test operations at one of said at least one test units to be executed independently from the determination of the starting times of the test operations at the others of said at least one test units; and means for providing said selected test operations to said logic unit at said determined start times via said at least one interface means to determine whether there are any logical failures associated with the logic unit so as to verify the logical design of the logic unit; wherein both the selection of test operations and the determination of their start times are executed pseudo-randomly and independently of each other at each of the at least one test units.

Claim 28

A system for the design verification of a logic unit where the logic unit comprises at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units comprise a set of test operations which are carried into execution by the logic unit to permit the determination of logical failures associated with the logic unit so as to verify the logical design of the logic unit; and wherein both selection of test operations and determination of their start times are executed randomly and independently of each other, and wherein the selection of a test operation is carried out by an operation select pointer, which is supplied with a pseudo-random number being generated by a modulo operation based on an initial pseudo-random number and a maximum number of test operations.

Claim 29

A system for the design verification of a logic unit where the logic unit comprises at least one interface means for external communication, and wherein at least one test unit is connected with the logic unit via one of the interface means, and wherein each of the test units comprise a set of test operations which are carried into execution by the logic unit to permit the determination of logical failures associated with the logic unit so as to verify the logical design of the logic unit; and wherein both selection of test operations and determination of their start times are executed randomly and independently of each other, and wherein the selection of a test operation is carried out by an operation select pointer, which is supplied with a pseudo-random number being generated by a modulo operation based on an initial pseudo-random number and a maximum number of test operations.