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US5568087A
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Pre-distorting linearization circuit
Assignee: European Space Agency
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Filing: 1995-06-12
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Granted: 1996-10-22
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Expires: 2015-06-12
Abstract
Abstract The invention concerns a pre-distorting linearization circuit, comprising a splitter circuit with an input forming the input of the linearization circuit and first and second outputs feeding first and second parallel stages respectively, of which at least one has a defined distortion characteristic, and a combining circuit receiving the signals provided by the first and second stages at first and second inputs respectively and having a recombination output. According to the invention, the first and second stages have first and second transistors respectively having different dimensions, which confer different non-linearity characteristics thereon, such that for the same voltage on the input of the linearization circuit, the first stage exhibits a higher degree of non-linearity than the second stage.
Inventors
- 👤 Giuliano Gatti
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:15
CPC Classifications
H; H04; H04B; H04B1/00; H04B1/62; H03; H03F; H03F1/00; H03F1/32; H03F1/3241; H03F1/3252; H03F1/3276
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
120 words
A pre-distorting linearization circuit, comprising a splitter circuit with an input forming the input of the linearization circuit and first and second outputs feeding first and second parallel stages respectively, of which at least one has a defined distortion characteristic, and a combining circuit receiving the signals provided by the first and second stages at first and second inputs respectively and having a recombination output which forms the output of the linearization circuit, wherein the first and second stages have first and second transistors respectively having different dimensions, which confer different non-linearity characteristics thereon, such that for the same voltage on the input of the linearization circuit, the first stage exhibits a higher degree of non-linearity than the second stage.
Claim 2
Dependent Claim
120 words
A pre-distorting linearization circuit, comprising a splitter circuit with an input forming the input of the linearization circuit and first and second outputs feeding first and second parallel stages respectively, of which at least one has a defined distortion characteristic, and a combining circuit receiving the signals provided by the first and second stages at first and second inputs respectively and having a recombination output which forms the output of the linearization circuit, wherein the first and second stages have first and second transistors respectively having different dimensions, which confer different non-linearity characteristics thereon, such that for the same voltage on the input of the linearization circuit, the first stage exhibits a higher degree of non-linearity than the second stage.
Claim 3
Dependent Claim
32 words
A circuit according to claim 1, wherein the first and second transistors are field effect transistors having first and second gates respectively, whose widths are in a given ratio other than unity.
Claim 4
Dependent Claim
13 words
A circuit according to claim 2, wherein said field effect transistors are MESFETs.
Claim 5
Dependent Claim
21 words
A circuit according to claim 3, wherein each of the MESFETs has a gate bias terminal and a drain bias terminal.
Claim 6
Dependent Claim
34 words
A circuit according to claim 2, wherein the ratio between the widths of the gates of the second and first transistors lies in the range 2 to 10 and is preferably equal to 4.
Claim 7
Dependent Claim
21 words
A circuit according to claim 1, wherein the splitter circuit and the combining circuit have a nominal impedance of 100 Ω.
Claim 8
Dependent Claim
135 words
A circuit according to claim 6, wherein the splitter circuit and the combining circuit each have a series branch comprising in succession a first, a second, and a third capacitor in series, forming an output branch for the splitter circuit and an input branch for the combining circuit, a first inductor having a first terminal connected to a first terminal of the second capacitor, a second inductor having a first terminal connected to a second terminal of the second capacitor, a fourth capacitor connected between the second terminals of the first and the second inductor and a resistor connected between the second terminal of the second inductor and a voltage supply terminal, the second terminal of the first inductor forming an input terminal for the splitter circuit and an output terminal for the combining circuit.
Claim 9
Dependent Claim
13 words
A circuit according to claim 1, wherein the first stage has a phase-shifter.
Claim 10
Dependent Claim
13 words
A circuit according to claim 8, wherein the phase-shifter is a delay line.
Claim 11
Dependent Claim
37 words
A circuit according to claim 8, wherein the splitter circuit, the combining circuit, and the first and second stages are on a first MMIC technology substrate, while the delay line is on a second MIC technology substrate.
References Cited (Backward Citations)
US4564816A
Cited
US5291148A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |