Patent US5568078A successfully refreshed from Google Patents.
US5568078A
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US
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Clock delay compensating and duty controlling apparatus of a phase-locked loop
Assignee: UTStarcom Korea Ltd
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Filing: 1995-06-05
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Granted: 1996-10-22
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Expires: 2015-06-05
Abstract
Abstract For clock delay compensation and duty control of a phase-locked loop in a decoder of a video signal receiving system, phases of two input clocks received into a phase comparative detector are compared to divide a reference clock from an oscillator of the phase comparative detector for obtaining a resultant phase error output in a divider in accordance with the result of the phase comparison, a duty ratio of the output clock therefrom is controlled in a duty controller to allow the phase comparative detector to be utilized free from the duty ratio of the clock, and a clock delay compensator performs correction of clock delay compensation of the system operated at high speed in the synchronized phase-locked loop, thereby controlling a duty ratio of a signal divided in the divider when determining accuracy, frequency and stabilization in the duty controller, and correcting an error in delay time by adding the clock delay compensator.
Inventors
- 👤 Seung Y. Lee
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:21
CPC Classifications
H; H04; H04N; H04N5/00; H04N5/76; H03; H03K; H03K5/00; H03K5/15; H03K5/15013; H03K5/156; H03K5/1565; H03L; H03L7/00; H03L7/06; H03L7/16; H03L7/18
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
294 words
A phase-locked loop circuit of a video signal receiving system comprising: an oscillating circuit which generates a reference oscillating clock, an L-dividing circuit which divides the reference clock from said oscillating circuit, a phase comparative detecting circuit which receives a first clock signal from said L-dividing circuit, a voltage-controlled oscillating circuit which is controlled by a second clock signal from said phase comparative detecting circuit, an M-dividing circuit which divides a third clock signal from said voltage-controlled oscillating circuit and passes it to the phase comparative detecting circuit, and a dividing circuit portion including at least one dividing circuit, said dividing circuit portion coupled to the voltage-controlled oscillating circuit to divide the third clock signal; a selecting circuit coupled between an output terminal of said oscillating circuit and an input terminal of said L-dividing circuit, said selecting circuit selecting said reference oscillating clock from said oscillating circuit and an external oscillating clock signal; a first duty controlling circuit coupled between an output terminal of said L-dividing circuit and a first input terminal of said phase comparative detecting circuit, said first duty controlling circuit controlling a duty ratio of said first clock signal received by said L-dividing circuit; a second duty controlling circuit coupled between an input terminal of said M-dividing circuit and a output of said voltage-controlled oscillating circuit, said second duty controlling circuit controlling a duty ratio of said third clock signal which is supplied to a second input terminal of said phase comparative detecting circuit through said M-dividing circuit; and a clock delay circuit portion coupled to said dividing circuit portion and said voltage-controlled oscillator circuit output, said clock delay circuit portion including at least one clock delay circuit to provide a delayed signal to an output of the phase-locked loop circuit.
Claim 2
Dependent Claim
294 words
A phase-locked loop circuit of a video signal receiving system comprising: an oscillating circuit which generates a reference oscillating clock, an L-dividing circuit which divides the reference clock from said oscillating circuit, a phase comparative detecting circuit which receives a first clock signal from said L-dividing circuit, a voltage-controlled oscillating circuit which is controlled by a second clock signal from said phase comparative detecting circuit, an M-dividing circuit which divides a third clock signal from said voltage-controlled oscillating circuit and passes it to the phase comparative detecting circuit, and a dividing circuit portion including at least one dividing circuit, said dividing circuit portion coupled to the voltage-controlled oscillating circuit to divide the third clock signal; a selecting circuit coupled between an output terminal of said oscillating circuit and an input terminal of said L-dividing circuit, said selecting circuit selecting said reference oscillating clock from said oscillating circuit and an external oscillating clock signal; a first duty controlling circuit coupled between an output terminal of said L-dividing circuit and a first input terminal of said phase comparative detecting circuit, said first duty controlling circuit controlling a duty ratio of said first clock signal received by said L-dividing circuit; a second duty controlling circuit coupled between an input terminal of said M-dividing circuit and a output of said voltage-controlled oscillating circuit, said second duty controlling circuit controlling a duty ratio of said third clock signal which is supplied to a second input terminal of said phase comparative detecting circuit through said M-dividing circuit; and a clock delay circuit portion coupled to said dividing circuit portion and said voltage-controlled oscillator circuit output, said clock delay circuit portion including at least one clock delay circuit to provide a delayed signal to an output of the phase-locked loop circuit.
Claim 3
Dependent Claim
45 words
The phase-locked loop circuit as claimed in claim 1, wherein said dividing circuit portion includes a plurality of dividing circuits, each receiving said third clock signal and said clock delay circuit portion compensates for different delay times of respective signals generated by said dividing circuits.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-22 | 2000-04-22 | 2000-10-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-22 | 2004-04-22 | 2004-10-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-22 | 2008-04-22 | 2008-10-22 | $7700.00 | Window Closed / Lapsed |