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US5564056A
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Method and apparatus for zero extension and bit shifting to preserve register parameters in a microprocessor utilizing register renaming
Assignee: Intel Corp
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Filing: 1994-11-02
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Granted: 1996-10-08
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Expires: 2014-11-02
Abstract
Abstract Register identification preservation in a microprocessor implementing register renaming. Multiplexing and control circuitry are implemented for manipulating data sources to be supplied to a microprocessor's functional units. The circuitry will generate zero extending for source data to an execution unit where a data source register specified is shorter than a general register size utilized by the microprocessor. Similarly, the multiplexing and control circuitry will shift bits of data from one location to another upon a source input to a functional unit in accordance with control signals designating such activity.
Inventors
- 👤 Michael A. Fetterman
- 👤 Andrew F. Glew
- 👤 Glenn J. Hinton
- 👤 David B. Papworth
- 👤 Robert P. Colwell
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 14:27
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/38; G06F9/3836; G06F9/3838; G06F9/384; G06F9/30003; G06F9/30007; G06F9/30036; G06F9/3824; G06F9/3826; G06F9/3828; G06F9/3842; G06F9/3854; G06F9/3856; G06F9/3885
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
161 words
An apparatus for zero extending source input data to a functional unit in a microprocessor comprising: an instruction dispatch mechanism for dispatching an instruction and source input data to the functional unit, the instruction dispatch mechanism also providing a zero extend control signal when the source input data is to be zero extended; bit selection logic disposed between the instruction dispatch mechamism and the front end of the functional unit, the bit selection logic for passing the source input data to the functional unit, the bit selection logic responsive to the zero extend control signal for providing the source input data zero extended to the functional unit; and a writeback bus coupled to the functional unit, the writeback bus configured to return result data from the functional unit, the writeback bus directly coupled to the bit selection logic for bypassing source inputs, wherein said bit selection logic is further configured to provide zero extended result data as the source input data.
Claim 2
Independent Claim
161 words
An apparatus for zero extending source input data to a functional unit in a microprocessor comprising: an instruction dispatch mechanism for dispatching an instruction and source input data to the functional unit, the instruction dispatch mechanism also providing a zero extend control signal when the source input data is to be zero extended; bit selection logic disposed between the instruction dispatch mechamism and the front end of the functional unit, the bit selection logic for passing the source input data to the functional unit, the bit selection logic responsive to the zero extend control signal for providing the source input data zero extended to the functional unit; and a writeback bus coupled to the functional unit, the writeback bus configured to return result data from the functional unit, the writeback bus directly coupled to the bit selection logic for bypassing source inputs, wherein said bit selection logic is further configured to provide zero extended result data as the source input data.
Claim 3
Dependent Claim
178 words
The apparatus of claim 1 wherein the functional unit comprises a first source input path and a second source input path, the first and second source input paths each for receiving source input data having low order bits and high order bits, the zero extend control signal comprising first and second source input path zero extend control signals, the bit selection logic comprising: first high order bit multiplexing logic through which the high order bits of the source input data for the first source input are passed; second high order bit multiplexing logic through which the high order bits of the source input data for the second source input are passed; and first zero value generating circuitry coupled to the inputs of the first and second high order bit multiplexing logic; the first high order bit multiplexing logic selecting a zero input in response to the first source input path zero extend control signal, and the second high order bit multiplexing logic selecting, a zero input in response to the second source input path zero extend control signal.
Claim 4
Dependent Claim
159 words
The apparatus of claim 2 wherein source input data includes middle order bits, the zero extend control signal further comprises first and second input path middle order bit zero extend control signals, the bit selection logic further comprising: first middle order bit multiplexing logic through which the middle order bits of the source input data for the first source input are passed; second middle order bit multiplexing logic through which the middle order bits of the source input data for the second source input are passed; and second zero value generating circuitry coupled to the inputs of the first and second middle order bit multiplexing logic, the first middle order bit multiplexing logic selecting a zero input in response to the first source input path middle order bit zero extend control signal, and the second middle order bit multiplexing logic selecting, a zero input in response to the second source input path middle order bit zero extend control signal.
Claim 5
Dependent Claim
37 words
The apparatus of claim 3 wherein source inputs to the functional unit are 32 bits, the high order bits comprising bits [16:31], the middle order bits comprising bits [8:15], and the low order bits comprising bits [0:7].
Claim 6
Dependent Claim
40 words
The apparatus of claim 3 wherein the instruction dispatch mechanism comprises a reservation station coupled to the functional unit through the bit selection logic, the reservation station for buffering instructions for dispatching and for buffering the zero extend control signals.
Claim 7
Dependent Claim
50 words
The apparatus of claim 5 further comprising a register alias table (RAT) for providing the zero extend control signals to the reservation station for buffering with an associated instruction, the RAT determining the status for the zero extend control signals based on the identity of the operands to the instruction.
Claim 8
Dependent Claim
36 words
The apparatus of claim 6 wherein the bit selection logic comprises circuitry for shifting the middle order bits of source input data to the low order bits of the source input path to the functional unit.
Claim 9
Dependent Claim
32 words
The apparatus of claim 7 wherein the bit selection logic comprises a low order bit multiplexing logic is coupled to receive both middle order and low order bits of source input data.
Claim 10
Dependent Claim
38 words
The apparatus of claim 8 wherein the low order bit multiplexing logic is coupled to receive a bit shift control signal from the reservation station, the reservation station buffering the bit shift control signal with an associated instruction.
Claim 11
Dependent Claim
77 words
The apparatus of claim 9 further comprising: a plurality of additional functional units coupled to the reservation station; and a plurality of additional writeback buses coupled to the plurality of additional functional units for returning result data from the additional functional units, the plurality of additional writeback buses directly coupled to the bit selection logic for bypassing source inputs; the bit selection logic selecting a source data input responsive to a control signal from the reservation station.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-08 | 2000-04-08 | 2000-10-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-08 | 2004-04-08 | 2004-10-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-08 | 2008-04-08 | 2008-10-08 | $7700.00 | Window Closed / Lapsed |