Superscalar processor having bypass circuit for directly transferring result of instruction execution between pipelines without being written to register file

Claim 1

A superscalar processing system for parallelly processing a plurality of instructions using a superscalar method, comprising: first and second instruction execution operating units; a register file having first and second read ports and first and second write ports; and first and second instruction decoders, said first and second instruction decoders responding to said first and second instruction execution operating units, respectively; said first instruction execution operating unit including: a first pipeline having a first terminal connected to said first write port, a first arithmetic and logic unit having an output port connected to a second terminal of said first pipeline, two two-input selector circuits for selectively receiving data to be processed in accordance with instructions, two flip-flop circuits, each positioned between respective ones of said two-input selector circuits and an input port of said first arithmetic and logic unit, and a first group of flip-flop circuits arranged on said first pipeline for storing data; said second instruction execution operating unit including: a second pipeline having a first terminal connected to said second write port, a second arithmetic and logic unit having an output port connected to a second terminal of said pipeline, two two-input selector circuits for selectively receiving data to be processed in accordance with instructions, two flip-flop circuits, each positioned between respective ones of said two-input selector circuits and an input port of said second arithmetic and logic unit, and a second group of flip-flop circuits arranged on said second pipeline for storing data; a first group of bypass circuits, each connecting said first pipeline to one of said two two-input selection circuits of said second instruction execution operating unit, for transferring data stored in said first group of flip-flop circuits to said one of said two two-input selection circuits of said second instruction execution operating unit; and a second group of bypass circuits, each connecting said second pipeline to one of said two two-input selection circuits of said first instruction execution operating unit, for transferring data stored in said second group of flip-flop circuits to said one of said two two-input selection circuits of said first instruction execution operating unit.