Method of fabricating InAs/GaSb/AlSb material system SRAM

Claim 1

A method of fabricating a static random access memory cell structure comprising the steps of: providing a GaAs substrate having a substantially planar surface; growing a buffer layer of superlattices on the surface of the substrate; forming a first InAs layer on the buffer layer, an AlSb layer on the first InAs layer, a second InAs layer on the AlSb layer, a first barrier layer of AlSb on the second InAs layer, an active layer of GaSb on the first barrier layer of AlSb, a second barrier layer of AlSb on the active layer of GaSb, and a third InAs layer on the second barrier layer of AlSb,; defining first and second contacts on the third InAs layer and depositing metal terminals on the defined first and second contacts; selectively etching the third InAs layer using the metal terminals as a mask; selectively etching the second barrier layer of AlSb, the active layer of GaSb, and the first barrier layer of AlSb using the metal terminals as a mask; selectively partially etching the second InAs layer to separate and define the structure into two resonant tunneling diodes; depositing an insulating layer over the entire structure after selectively partially etching the second InAs layer; opening at least one bottom contact region on a surface of the partially etched second InAs layer adjacent one of the defined resonant tunneling diodes by selectively removing a portion of the insulating layer; selectively etching any remaining portion of the second InAs layer in the bottom contact region; selectively etching the AlSb layer in the bottom contact region; selectively partially etching the first InAs layer in the bottom contact region to expose a surface of the first InAs layer; and depositing a third metal terminal on the exposed surface of the first InAs layer.

Claim 2

A method of fabricating a static random access memory cell structure comprising the steps of: providing a GaAs substrate having a substantially planar surface; growing a buffer layer of superlattices on the surface of the substrate; forming a first InAs layer on the buffer layer, an AlSb layer on the first InAs layer, a second InAs layer on the AlSb layer, a first barrier layer of AlSb on the second InAs layer, an active layer of GaSb on the first barrier layer of AlSb, a second barrier layer of AlSb on the active layer of GaSb, and a third InAs layer on the second barrier layer of AlSb,; defining first and second contacts on the third InAs layer and depositing metal terminals on the defined first and second contacts; selectively etching the third InAs layer using the metal terminals as a mask; selectively etching the second barrier layer of AlSb, the active layer of GaSb, and the first barrier layer of AlSb using the metal terminals as a mask; selectively partially etching the second InAs layer to separate and define the structure into two resonant tunneling diodes; depositing an insulating layer over the entire structure after selectively partially etching the second InAs layer; opening at least one bottom contact region on a surface of the partially etched second InAs layer adjacent one of the defined resonant tunneling diodes by selectively removing a portion of the insulating layer; selectively etching any remaining portion of the second InAs layer in the bottom contact region; selectively etching the AlSb layer in the bottom contact region; selectively partially etching the first InAs layer in the bottom contact region to expose a surface of the first InAs layer; and depositing a third metal terminal on the exposed surface of the first InAs layer.

Claim 5

A method of fabricating a static random access memory structure comprising the steps of: providing a GaAs substrate having a substantially planar surface; epitaxially growing a buffer layer including superlattices on the surface of the substrate; epitaxially growing a first n+ InAs layer on the buffer layer, an AlSb layer on the first n+ InAs layer, a second n+InAs layer on the AlSb layer, a first n- InAs layer on the second n+ InAs layer, a first undoped InAs layer on the first n- InAs layer, a first barrier layer of AlSb on the first undoped InAs layer, an active layer of GaSb on the first barrier layer of AlSb, a second barrier layer of AlSb on the active layer of GaSb, a second undoped layer of InAs on the second barrier layer of AlSb, a second n- InAs layer on the second undoped layer of InAs, and a third n+ InAs layer on the second n- InAs layer; defining first and second contacts on the third n+ InAs layer and depositing metal terminals on the defined first and second contacts; selectively etching the third n+ InAs layer, the second n- InAs layer, and the second undoped layer of InAs using the metal terminals as a mask; selectively etching the second barrier layer of AlSb, the active layer of GaSb, and the first barrier layer of AlSb using the metal terminals as a mask; selectively partially etching the first undoped InAs layer and the first n- InAs layer to separate and define the structure into two resonant tunneling diodes; depositing an insulating layer over the entire structure after selectively partially etching the first undoped InAs layer and the first n- InAs layer; opening at least one bottom contact region on a surface of the partially etched first n- InAs layer adjacent one of the defined resonant tunneling diodes by selectively removing a port ion of the insulating layer; selectively etching any remaining portion of the first n- InAs layer in the bottom contact region and the second n+ InAs layer; selectively etching the AlSb layer in the bottom contact region; selectively partially etching the first n+ InAs layer in the bottom contact region to expose a surface of the first n+ InAs layer; and depositing a third metal terminal on the exposed surface of the first n+ InAs layer.

Claim 6

A method of fabricating a static random access memory structure comprising the steps of: providing a GaAs substrate having a substantially planar surface; epitaxially growing a buffer layer including superlattices on the surface of the substrate; epitaxially growing a first n+ InAs layer on the buffer layer, an AlSb layer on the first n+ InAs layer, a second n+InAs layer on the AlSb layer, a first n- InAs layer on the second n+ InAs layer, a first undoped InAs layer on the first n- InAs layer, a first barrier layer of AlSb on the first undoped InAs layer, an active layer of GaSb on the first barrier layer of AlSb, a second barrier layer of AlSb on the active layer of GaSb, a second undoped layer of InAs on the second barrier layer of AlSb, a second n- InAs layer on the second undoped layer of InAs, and a third n+ InAs layer on the second n- InAs layer; defining first and second contacts on the third n+ InAs layer and depositing metal terminals on the defined first and second contacts; selectively etching the third n+ InAs layer, the second n- InAs layer, and the second undoped layer of InAs using the metal terminals as a mask; selectively etching the second barrier layer of AlSb, the active layer of GaSb, and the first barrier layer of AlSb using the metal terminals as a mask; selectively partially etching the first undoped InAs layer and the first n- InAs layer to separate and define the structure into two resonant tunneling diodes; depositing an insulating layer over the entire structure after selectively partially etching the first undoped InAs layer and the first n- InAs layer; opening at least one bottom contact region on a surface of the partially etched first n- InAs layer adjacent one of the defined resonant tunneling diodes by selectively removing a port ion of the insulating layer; selectively etching any remaining portion of the first n- InAs layer in the bottom contact region and the second n+ InAs layer; selectively etching the AlSb layer in the bottom contact region; selectively partially etching the first n+ InAs layer in the bottom contact region to expose a surface of the first n+ InAs layer; and depositing a third metal terminal on the exposed surface of the first n+ InAs layer.