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US5345097A Expired / Lapsed US ⏱️ 0.0 years remaining

Heterojunction bipolar transistor including collector region of InP and method of fabricating the same

Assignee: Panasonic Holdings Corp
•
Filing: 1992-09-23
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Granted: 1994-09-06
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Expires: 2012-09-23
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Abstract

Abstract A heterojunction bipolar transistor includes a collector region made of first-conduction-type InP. and a base region connected to the collector region and made of second-conduction-type In x (Ga y Al 1-y ) 1-x As where the letters "x" and "y" denote predetermined atomic fractions. The atomic fraction "x" is in the range of 0.52 to 0.53. The atomic fraction "y" is in the range of 0.35 to 0.72.

Inventors

  • 👤 Atsushi Nakagawa

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 16:10
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/80; H10D10/821

Claims Analysis

Total Claims: 7
Claim 1
Independent Claim 103 words
A heterojunction bipolar transistor comprising: a collector region made of first-conduction-type InP; and a base region connected to the collector region and made of second-conduction-type In x (Ga y Al 1-y ) 1-x As where the letters "x" and "y" denote predetermined atomic fractions, wherein the atomic fraction "x" is in the range of 0.52 to 0.53 and the atomic fraction "y" is in the range of 0.35 to 0.72, further including a semi-insulating substrate of InP, a subcollector region of first conduction type In x Ga 1-x As on said substrate, and wherein said collector region is situated on said subcollector region.
Claim 2
Dependent Claim 103 words
A heterojunction bipolar transistor comprising: a collector region made of first-conduction-type InP; and a base region connected to the collector region and made of second-conduction-type In x (Ga y Al 1-y ) 1-x As where the letters "x" and "y" denote predetermined atomic fractions, wherein the atomic fraction "x" is in the range of 0.52 to 0.53 and the atomic fraction "y" is in the range of 0.35 to 0.72, further including a semi-insulating substrate of InP, a subcollector region of first conduction type In x Ga 1-x As on said substrate, and wherein said collector region is situated on said subcollector region.
Claim 3
Dependent Claim 33 words
The heterojunction bipolar transistor of claim 1, wherein the atomic fraction "x" is in the range of 0.524 to 0.526 and the atomic fraction "y" is in the range of 0.485 to 0.505.
Claim 4
Dependent Claim 62 words
The heterojunction bipolar transistor of claim 1, further comprising a first emitter region made of first-conduction-type InP and connected to the base region, and a second emitter region connected to the first emitter region and made of first-conduction-type In x (Ga y Al 1-y ) 1-x As, wherein the first emitter region extends between the base region and the second emitter region.
Claim 5
Independent Claim 124 words
A method of fabricating a heterojunction bipolar transistor, comprising the steps of: forming a collector region from first-conduction-type InP; and forming a base region from second-conduction-type In x (Ga y Al 1-y ) 1-x As where the letters "x" and "y" denote predetermined atomic fractions, wherein the atomic fraction "x" is in the range of 0.52 to 0.53 and the atomic fraction "y" is in the range of 0.35 to 0.72, the base region being connected to the collector region, wherein said step of forming a collector region further comprises the steps of: forming a semi-insulating substrate of InP, forming a subcollector region of first conduction type In x Ga 1-x As on said substrate, and forming said collector region on said subcollector region.
Claim 6
Independent Claim 124 words
A method of fabricating a heterojunction bipolar transistor, comprising the steps of: forming a collector region from first-conduction-type InP; and forming a base region from second-conduction-type In x (Ga y Al 1-y ) 1-x As where the letters "x" and "y" denote predetermined atomic fractions, wherein the atomic fraction "x" is in the range of 0.52 to 0.53 and the atomic fraction "y" is in the range of 0.35 to 0.72, the base region being connected to the collector region, wherein said step of forming a collector region further comprises the steps of: forming a semi-insulating substrate of InP, forming a subcollector region of first conduction type In x Ga 1-x As on said substrate, and forming said collector region on said subcollector region.
Claim 7
Dependent Claim 26 words
The heterojunction transistor of claim 1, further comprising a collector electrode on said subcollector region, said collector electrode surrounding and in contact with said collector region.

References Cited (Backward Citations)

JPS61203675A Cited
JPS62139354A Cited
US4821082A Cited
US5010382A Cited
JPH02280338A Cited
US5153461A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-09-05 1998-03-07 1998-09-06 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-09-05 2002-03-07 2002-09-06 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-09-05 2006-03-07 2006-09-06 $7700.00 Window Closed / Lapsed

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