US5561779A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Processor board having a second level writeback cache system and a third level writethrough cache system which stores exclusive state information for use in a multiprocessor computer system
Assignee: Hewlett Packard Development Co LP
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Filing: 1994-05-04
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Granted: 1996-10-01
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Expires: 2014-05-04
Abstract
Abstract A computer system which utilizes processor boards including a first level cache system integrated with the microprocessor, a second level external cache system and a third level external cache system. The second level cache system is a conventional, high speed, SRAM-based, writeback cache system. The third level cache system is a large, writethrough cache system developed using conventional DRAMs as used in the main memory subsystem of the computer system. The three cache systems are arranged between the CPU and the host bus in a serial fashion. Because of the large size of the third level cache, a high hit rate is developed so that operations are not executed on the host bus but are completed locally on the processor board, reducing the use of the host bus by an individual processor board. This allows additional processor boards to be installed in the computer system without saturating the host bus. The third level cache system is organized as a writethrough cache. However, the shared or exclusive status of any cached data is also stored. If the second level cache performs a write allocate cycle and the data is exclusive in the third level cache, the data is provided directly from the third level cache, without requiring an access to main memory, reducing the use of the host bus.
Inventors
- 👤 Michael T. Jackson
- 👤 Walter G. Fry
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 17:41
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0811; G06F12/0815; G06F12/0831
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
104 words
A processor board for use in a computer system, the processor board comprising: a microprocessor; a first level cache system connected to said microprocessor; a second level cache system connected to said first level cache system and larger than said first level cache system, said second level cache system being a writeback cache and operating according to a modified, exclusive, shared, invalid protocol; and a third level cache system connected to said second level cache system and larger than said second level cache system, said third level cache system being a writethrough cache and including storage of shared and exclusive status of cached data.
Claim 2
Dependent Claim
104 words
A processor board for use in a computer system, the processor board comprising: a microprocessor; a first level cache system connected to said microprocessor; a second level cache system connected to said first level cache system and larger than said first level cache system, said second level cache system being a writeback cache and operating according to a modified, exclusive, shared, invalid protocol; and a third level cache system connected to said second level cache system and larger than said second level cache system, said third level cache system being a writethrough cache and including storage of shared and exclusive status of cached data.
Claim 3
Dependent Claim
22 words
The processor board of claim 1, wherein said microprocessor and said first level cache system are contained in a single integrated circuit.
Claim 4
Dependent Claim
26 words
The processor board of claim 1, wherein a processor operation serially traverses said first, second and third cache systems if not handled by said cache systems.
Claim 5
Dependent Claim
41 words
The processor board of claim 1, wherein write allocation operations of said second level cache system are provided by said third level cache system if the data is contained in said third level cache system and said data status is exclusive.
Claim 6
Dependent Claim
182 words
A multiprocessor computer system comprising: a bus for transferring operational cycles; a memory system connected to said bus; a plurality of connectors connected to said bus to allow connection to said bus; and a plurality of processor boards installed in said plurality of connectors and connected to said bus, each of said processor boards capable of controlling said bus to perform operational cycles and each of said processor boards monitoring operational cycles on said bus when not controlling said bus, wherein at least one of said plurality of processor boards includes: a microprocessor; a first level cache system connected to said microprocessor; a second level cache system connected to said first level cache system and larger than said first level cache system, said second level cache system being a writeback cache and operating according to a modified, exclusive, shared, invalid protocol; and a third level cache system connected to said second level cache system and larger than said second level cache system, said third level cache system being a writethrough cache and including storage of shared and exclusive status of cached data.
Claim 7
Dependent Claim
182 words
A multiprocessor computer system comprising: a bus for transferring operational cycles; a memory system connected to said bus; a plurality of connectors connected to said bus to allow connection to said bus; and a plurality of processor boards installed in said plurality of connectors and connected to said bus, each of said processor boards capable of controlling said bus to perform operational cycles and each of said processor boards monitoring operational cycles on said bus when not controlling said bus, wherein at least one of said plurality of processor boards includes: a microprocessor; a first level cache system connected to said microprocessor; a second level cache system connected to said first level cache system and larger than said first level cache system, said second level cache system being a writeback cache and operating according to a modified, exclusive, shared, invalid protocol; and a third level cache system connected to said second level cache system and larger than said second level cache system, said third level cache system being a writethrough cache and including storage of shared and exclusive status of cached data.
Claim 8
Dependent Claim
41 words
The computer system of claim 5, wherein write allocation operations of said second level cache system are provided by said third level cache system if the data is contained in said third level cache system and said data status is exclusive.
Claim 9
Dependent Claim
29 words
The computer system of claim 5, wherein said microprocessor and said first level cache system of said at least one processor board are contained in a single integrated circuit.
Claim 10
Dependent Claim
33 words
The computer system of claim 5, wherein a processor operation serially traverses said first, second and third cache systems of said at least one processor board if not handled by said cache systems.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-10-01 | 2000-04-01 | 2000-10-01 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-10-01 | 2004-04-01 | 2004-10-01 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-10-01 | 2008-04-01 | 2008-10-01 | $7700.00 | Window Closed / Lapsed |