Logarithmic amplifier employing cascaded full-wave rectifiers including emitter-coupled pairs with unbalanced emitter degeneration as logarithmic elements

Claim 2

A logarithmic amplification circuit for amplifying an initial input signal comprising: (a) a differential amplifier producing an output signal in response to said initial input signal; (b) a first full-wave rectifier for rectifying said initial input signal and for generating a first rectified output signal, said first full-wave rectifier including identical first and second half-wave rectifiers connected so that said initial input signal is applied to said first and second half-wave rectifiers inverse in phase relative to each other; said first and second half-wave rectifiers including respective differential transistor pairs consisting of first and second transistors, and third and fourth transistors, respectively, wherein emitter areas of said first and second transistors are equal, and emitter areas of said third and fourth transistors are equal; wherein each of said second and third transistors has an emitter resistor, said second and third transistors being connected together by their respective collectors, said first and fourth transistors being connected together by their respective collectors, said first and third transistors being connected together by their respective bases, said second and fourth transistors being connected together by their respective bases, and wherein said initial input signal is received between said bases of said first and third transistors and said bases of said second and fourth transistors, and (c) a second full-wave rectifier for rectifying said output signal of said differential amplifier and for generating a second rectified output signal, said second full-wave rectifier including identical third and fourth half-wave rectifiers connected so that said output signal of said differential amplifier is applied to said third and fourth half-wave rectifiers inverse in phase relative to each other, said third and fourth half-wave rectifiers including respective differential transistor pairs consisting of fifth and sixth transistors, and seventh and eighth transistors, respectively, wherein emitter areas of said fifth and sixth transistors are equal and emitter areas of said seventh and eighth transistors are equal; wherein each of said sixth and seventh transistors has an emitter resistor, said sixth and seventh transistors being connected together by their respective collectors, said fifth and eighth transistors being connected together by their respective collectors, said fifth and seventh transistors being connected together by their respective bases, said sixth and eighth transistors being connected together by their respective bases, and wherein said output signal of said differential amplifier is received between said bases of said fifth and seventh transistors and said bases of said sixth and eighth transistors; and (d) an adder for adding the first and second rectified output signals of said first and second full-wave rectifiers.

Claim 3

A logarithmic amplification circuit for amplifying an initial input signal comprising: (a) a differential amplifier producing an output signal in response to said initial input signal; (b) a first logarithmic element comprising a first plurality of full-wave rectifiers for rectifying said initial input signal and for generating a first rectified output signal, each of said plurality of full-wave rectifiers comprising: identical first and second half-wave rectifiers, each including respective differential transistor pairs consisting of first and second transistors, and third and fourth transistors, respectively, wherein emitter areas of said first and second transistors are equal and emitter areas of said third and fourth transistors are equal; wherein each of said second and third transistors has an emitter resistor, said second and third transistors being connected together by their respective collectors, said first and fourth transistors being connected together by their respective collectors, said first and third transistors being connected together by their respective bases, said second and fourth transistors being connected together by their respective bases, each of said plurality of said full-wave rectifiers receiving said initial input signal between said bases of each of said first and third transistors and said bases of each of said second and fourth transistors, and first constant current sources for supplying electric currents to said first and second half-wave rectifiers, respectively, wherein each of said full-wave rectifiers has a unique product of a resistance value of said emitter resistor and a current value of said constant current source; (c) a second logarithmic element comprising a second plurality of full-wave rectifiers for rectifying said output signal of said differential amplifier and for generating a second rectified output signal, each of said second plurality of full-wave rectifiers including: identical third and fourth half-wave rectifiers, each including respective differential transistor pairs consisting of fifth and sixth transistors, and seventh and eighth transistors, respectively, wherein emitter areas of said fifth and sixth transistors are equal and emitter areas of said seventh and eighth transistors are equal; wherein each of said sixth and seventh transistors has an emitter resistor, said sixth and seventh transistors being connected together by their respective collectors, said fifth and eighth transistors being connected together by their respective collectors, said fifth and seventh transistors being connected together by their respective bases, said sixth and eighth transistors being connected together by their respective bases, each of said second plurality of said full-wave rectifiers receiving said output signal of said differential amplifier between said bases of each of said fifth and seventh transistors and said bases of each of said sixth and eighth transistors; and second constant current sources for supplying electric currents to said third and fourth half-wave rectifiers; wherein each of said third and fourth half-wave rectifiers has a unique product of resistance value of an emitter resistor and a current value of said second constant current source; and (d) an adder for adding said first and second rectified output signals of said first and second logarithmic elements.

Claim 4

A logarithmic amplification circuit for amplifying an initial input signal comprising: (a) a differential amplifier producing an output signal in response to said initial input signal; (b) a first logarithmic element comprising a first plurality of full-wave rectifiers for rectifying said initial input signal and for generating a first rectified output signal, each of said plurality of full-wave rectifiers comprising: identical first and second half-wave rectifiers, each including respective differential transistor pairs consisting of first and second transistors, and third and fourth transistors, respectively, wherein emitter areas of said first and second transistors are equal and emitter areas of said third and fourth transistors are equal; wherein each of said second and third transistors has an emitter resistor, said second and third transistors being connected together by their respective collectors, said first and fourth transistors being connected together by their respective collectors, said first and third transistors being connected together by their respective bases, said second and fourth transistors being connected together by their respective bases, each of said plurality of said full-wave rectifiers receiving said initial input signal between said bases of each of said first and third transistors and said bases of each of said second and fourth transistors, and first constant current sources for supplying electric currents to said first and second half-wave rectifiers, respectively, wherein each of said full-wave rectifiers has a unique product of a resistance value of said emitter resistor and a current value of said constant current source; (c) a second logarithmic element comprising a second plurality of full-wave rectifiers for rectifying said output signal of said differential amplifier and for generating a second rectified output signal, each of said second plurality of full-wave rectifiers including: identical third and fourth half-wave rectifiers, each including respective differential transistor pairs consisting of fifth and sixth transistors, and seventh and eighth transistors, respectively, wherein emitter areas of said fifth and sixth transistors are equal and emitter areas of said seventh and eighth transistors are equal; wherein each of said sixth and seventh transistors has an emitter resistor, said sixth and seventh transistors being connected together by their respective collectors, said fifth and eighth transistors being connected together by their respective collectors, said fifth and seventh transistors being connected together by their respective bases, said sixth and eighth transistors being connected together by their respective bases, each of said second plurality of said full-wave rectifiers receiving said output signal of said differential amplifier between said bases of each of said fifth and seventh transistors and said bases of each of said sixth and eighth transistors; and second constant current sources for supplying electric currents to said third and fourth half-wave rectifiers; wherein each of said third and fourth half-wave rectifiers has a unique product of resistance value of an emitter resistor and a current value of said second constant current source; and (d) an adder for adding said first and second rectified output signals of said first and second logarithmic elements.

Claim 5

A logarithmic amplification circuit for amplifying an initial input signal comprising: (a) n differential amplifiers cascade connected, a first one of said n amplifiers producing an output signal in response to said initial input signal, and the remaining n-1 of said n amplifiers respectively producing output signals in response to an amplified output signal by a preceding one of said amplifiers, wherein n is an integer greater than or equal to two; (b) n+1 full-wave rectifiers, a first one of said n+1 full-wave rectifiers rectifying said initial input signal and producing a first rectified output signal, and the remaining n of said n+1 full-wave rectifiers respectively rectifying said output signals of said n differential amplifiers and producing n respective rectified signals, wherein each of said n+1 full-wave rectifiers comprises identical first and second half-wave rectifiers connected so that said initial input signal is applied to said first and second half-wave rectifiers inverse in phase relative to each other, said first and second half-wave rectifiers including respective differential transistor pairs consisting of first and second transistors, and third and fourth transistors, respectively, wherein emitter areas of said first and second transistors are equal and emitter areas of said third and fourth transistors are equal; wherein each of said second and third transistors has an emitter resistor, said second and third transistors being connected together by their respective collectors, said first and fourth transistors being connected together by their respective collectors, said first and third transistors being connected together by their respective bases, said second and fourth transistors being connected together by their respective bases, and wherein said initial input signal is received between said bases of said first and third transistors and said bases of said second and fourth transistors of said full-wave rectifier which rectifies said initial input signal, and said output signals of said n differential amplifiers are respectively received between said bases of said first and third transistors and said bases of said second and fourth transistors of said n full-wave rectifiers; and (c) an adder for adding said rectified output signals of said n+1 full-wave rectifiers.

Claim 6

A logarithmic amplification circuit for amplifying an initial input signal comprising: (a) n differential amplifiers cascade connected, a first one of said n amplifiers producing an output signal in response to said initial input signal, and the remaining n-1 of said n amplifiers respectively producing output signals in response to an amplified output signal by a preceding one of said amplifiers, wherein n is an integer greater than or equal to two; (b) n+1 full-wave rectifiers, a first one of said n+1 full-wave rectifiers rectifying said initial input signal and producing a first rectified output signal, and the remaining n of said n+1 full-wave rectifiers respectively rectifying said output signals of said n differential amplifiers and producing n respective rectified signals, wherein each of said n+1 full-wave rectifiers comprises identical first and second half-wave rectifiers connected so that said initial input signal is applied to said first and second half-wave rectifiers inverse in phase relative to each other, said first and second half-wave rectifiers including respective differential transistor pairs consisting of first and second transistors, and third and fourth transistors, respectively, wherein emitter areas of said first and second transistors are equal and emitter areas of said third and fourth transistors are equal; wherein each of said second and third transistors has an emitter resistor, said second and third transistors being connected together by their respective collectors, said first and fourth transistors being connected together by their respective collectors, said first and third transistors being connected together by their respective bases, said second and fourth transistors being connected together by their respective bases, and wherein said initial input signal is received between said bases of said first and third transistors and said bases of said second and fourth transistors of said full-wave rectifier which rectifies said initial input signal, and said output signals of said n differential amplifiers are respectively received between said bases of said first and third transistors and said bases of said second and fourth transistors of said n full-wave rectifiers; and (c) an adder for adding said rectified output signals of said n+1 full-wave rectifiers.

Claim 7

A logarithmic amplification circuit for amplifying an initial input signal comprising: (a) n differential amplifiers cascade connected, a first one of said n amplifiers producing an output signal in response to said initial input signal, and the remaining n-1 of said amplifiers respectively producing output signals in response to an amplified output signal by a preceding one of said amplifiers, wherein n is an integer greater than or equal to two; (b) n+1 logarithmic full-wave rectifiers, a first one of said n+1 full-wave rectifiers rectifying said initial input signal and producing a first rectified output signal, and the remaining n of said n+1 full-wave rectifiers respectively rectifying said output signals of said n differential amplifiers and producing n respective rectified signals, wherein each of said n+1 logarithmic full-wave rectifiers comprises a plurality of full-wave rectifiers, a first one of said n+1 logarithmic full-wave rectifiers rectifying said initial input signal and generating a rectified output signal, and the remaining n of said n+1 logarithmic full-wave rectifiers respectively rectifying said output signals of said n differential amplifiers and generating n respective rectified output signals, and wherein each of said plurality of said full-wave rectifiers comprises identical first and second half-wave rectifiers connected so that said initial input signal is applied to said first and second half-wave rectifiers inverse in phase relative to each other, said first and second half-wave rectifiers including: respective differential transistor pairs consisting of first and second transistors, and third and fourth transistors, respectively, wherein emitter areas of said first and second transistors are equal and emitter areas of said third and fourth transistors are equal; wherein each of said second and third transistors has an emitter resistor, said second and third transistors being connected together by their respective collectors, said first and fourth transistors being connected together by their respective collectors, said first and third transistors being connected together by their respective bases, said second and fourth transistors being connected together by their respective bases, and wherein said initial input signal is concurrently received between said bases of said first and third transistors and said bases of said second and fourth transistors of said respective full-wave rectifiers of said first one of said n+1 logarithmic full-wave rectifiers, and wherein said output signal of each of said n differential amplifiers is concurrently received between said bases of said first and third transistors and said bases of said second and fourth transistors of said respective full-wave rectifiers of each of the remaining n of said n+1 logarithmic full-wave rectifiers, and constant current sources for supplying electric currents to each of said first and second half-wave rectifiers, respectively; wherein each of said plurality of full-wave rectifiers in said n+1 logarithmic full-wave rectifiers has a unique product of a resistance value of said respective emitter resistors and a current value of said respective constant current sources; and (c) an adder for adding the rectified output signals from said n+1 logarithmic full-wave rectifiers.

Claim 8

A logarithmic amplification circuit for amplifying an initial input signal comprising: (a) n differential amplifiers cascade connected, a first one of said n amplifiers producing an output signal in response to said initial input signal, and the remaining n-1 of said amplifiers respectively producing output signals in response to an amplified output signal by a preceding one of said amplifiers, wherein n is an integer greater than or equal to two; (b) n+1 logarithmic full-wave rectifiers, a first one of said n+1 full-wave rectifiers rectifying said initial input signal and producing a first rectified output signal, and the remaining n of said n+1 full-wave rectifiers respectively rectifying said output signals of said n differential amplifiers and producing n respective rectified signals, wherein each of said n+1 logarithmic full-wave rectifiers comprises a plurality of full-wave rectifiers, a first one of said n+1 logarithmic full-wave rectifiers rectifying said initial input signal and generating a rectified output signal, and the remaining n of said n+1 logarithmic full-wave rectifiers respectively rectifying said output signals of said n differential amplifiers and generating n respective rectified output signals, and wherein each of said plurality of said full-wave rectifiers comprises identical first and second half-wave rectifiers connected so that said initial input signal is applied to said first and second half-wave rectifiers inverse in phase relative to each other, said first and second half-wave rectifiers including: respective differential transistor pairs consisting of first and second transistors, and third and fourth transistors, respectively, wherein emitter areas of said first and second transistors are equal and emitter areas of said third and fourth transistors are equal; wherein each of said second and third transistors has an emitter resistor, said second and third transistors being connected together by their respective collectors, said first and fourth transistors being connected together by their respective collectors, said first and third transistors being connected together by their respective bases, said second and fourth transistors being connected together by their respective bases, and wherein said initial input signal is concurrently received between said bases of said first and third transistors and said bases of said second and fourth transistors of said respective full-wave rectifiers of said first one of said n+1 logarithmic full-wave rectifiers, and wherein said output signal of each of said n differential amplifiers is concurrently received between said bases of said first and third transistors and said bases of said second and fourth transistors of said respective full-wave rectifiers of each of the remaining n of said n+1 logarithmic full-wave rectifiers, and constant current sources for supplying electric currents to each of said first and second half-wave rectifiers, respectively; wherein each of said plurality of full-wave rectifiers in said n+1 logarithmic full-wave rectifiers has a unique product of a resistance value of said respective emitter resistors and a current value of said respective constant current sources; and (c) an adder for adding the rectified output signals from said n+1 logarithmic full-wave rectifiers.

Claim 9

A logarithmic amplifier for amplifying an initial input signal, comprising: (a) an amplifier for amplifying an input signal and for outputting an amplified input signal; (b) a first logarithmic element for rectifying said initial input signal and for producing an output signal which varies substantially logarithmically as a function of said initial input signal, wherein said first logarithmic element comprises a plurality of full-wave rectifiers receiving said initial input signal, each of said full-wave rectifiers including two identical half-wave rectifiers, wherein each of said plurality of full-wave rectifiers has a unique operating range to produce a plurality of different rectified output signals in response to said initial input signal; (c) a second logarithmic element for rectifying said amplified input signal from said amplifier and for producing an amplified output signal which varies substantially logarithmically as a function of said amplified input signal, wherein said second logarithmic element comprises: a plurality of full-wave rectifiers receiving said amplified input signal, each of said full-wave rectifiers including two identical half-wave rectifiers, each comprising differential transistor pairs, emitter areas of each transistor of said differential transistor pairs having the same emitter area, wherein each of said plurality of full-wave rectifiers has a unique operating range to produce a plurality of different rectified output signals in response to said amplified input signal; and an adding means for adding said plurality of said rectified output signals from said first and second logarithmic elements.

Claim 10

A logarithmic amplifier for amplifying an initial input signal, comprising: (a) an amplifier for amplifying an input signal and for outputting an amplified input signal; (b) a first logarithmic element for rectifying said initial input signal and for producing an output signal which varies substantially logarithmically as a function of said initial input signal, wherein said first logarithmic element comprises a plurality of full-wave rectifiers receiving said initial input signal, each of said full-wave rectifiers including two identical half-wave rectifiers, wherein each of said plurality of full-wave rectifiers has a unique operating range to produce a plurality of different rectified output signals in response to said initial input signal; (c) a second logarithmic element for rectifying said amplified input signal from said amplifier and for producing an amplified output signal which varies substantially logarithmically as a function of said amplified input signal, wherein said second logarithmic element comprises: a plurality of full-wave rectifiers receiving said amplified input signal, each of said full-wave rectifiers including two identical half-wave rectifiers, each comprising differential transistor pairs, emitter areas of each transistor of said differential transistor pairs having the same emitter area, wherein each of said plurality of full-wave rectifiers has a unique operating range to produce a plurality of different rectified output signals in response to said amplified input signal; and an adding means for adding said plurality of said rectified output signals from said first and second logarithmic elements.

Claim 11

A logarithmic amplifier as claimed in claim 5, wherein each of said full-wave rectifiers includes two identical emitter-coupled transistor pairs with unbalanced emitter degeneration through emitter-degeneration resistors, and wherein each of said emitter-degeneration resistor is unique for each of said plurality of full-wave rectifiers.

Claim 12

A logarithmic amplifier as claimed in claim 6, wherein said amplifier is a differential amplifier for outputting a differential output signal as said amplified input signal, said full-wave rectifiers being coupled to said differential amplifier to receive said differential output signal, on their respective differential input terminals.

Claim 13

A logarithmic amplifier as claimed in claim 7, wherein each of said half-wave rectifiers further includes a constant current source for driving said emitter-coupled transistor pair with unbalanced emitter-degeneration; and wherein, for each of said plurality of said full-wave rectifiers, the product of a resistance value of said emitter-degeneration resistor and a current value of said constant current source is unique.

Claim 14

A logarithmic amplifier comprising: a plurality of M cascaded amplifier stages for respectively amplifying an input signal to produce respective amplified output signals; a plurality of M logarithmic elements for generating intermediate logarithmic output signals in response to respective ones of said amplified output signals produced by said plurality of M cascaded amplifiers, each of said M logarithmic elements having at least two rectifiers for generating said intermediate logarithmic output signals, each of said rectifiers comprising a pair of differential transistors wherein emitter areas of transistors in each of said pair of differential transistors are substantially equal; and an adder for adding said intermediate logarithmic output signals generated by said plurality of M logarithmic elements.

Claim 15

A logarithmic amplifier comprising: a plurality of M cascaded amplifier stages for respectively amplifying an input signal to produce respective amplified output signals; a plurality of M logarithmic elements for generating intermediate logarithmic output signals in response to respective ones of said amplified output signals produced by said plurality of M cascaded amplifiers, each of said M logarithmic elements having at least two rectifiers for generating said intermediate logarithmic output signals, each of said rectifiers comprising a pair of differential transistors wherein emitter areas of transistors in each of said pair of differential transistors are substantially equal; and an adder for adding said intermediate logarithmic output signals generated by said plurality of M logarithmic elements.

Claim 16

A logarithmic amplifier as claimed in claim 9, wherein said intermediate logarithmic output signals generated by said logarithmic elements are composed of a plurality of signal components, and wherein said adder further adds said signal components in adding said intermediate logarithmic output signals from said logarithmic elements.

Claim 17

A logarithmic amplifier as claimed in claim 10, further comprising an additional logarithmic element for generating a logarithmic output signal in response to an initial input signal for said logarithmic amplifier.

Claim 18

A logarithmic amplifier as claimed in claim 11, wherein said at least two rectifiers are half-wave rectifiers whose input ends are cross-coupled and whose output ends are connected in parallel.