US5070303A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Logarithmic amplifier/detector delay compensation
Assignee: Telefonaktiebolaget LM Ericsson AB
•
Filing: 1990-08-21
•
Granted: 1991-12-03
•
Expires: 2010-08-21
Abstract
Abstract An amplifier/detector chain logarithmically amplifies an input signal as well as compensates for delays generated by necessary bandwidth restrictions. A plurality of amplifiers are connected in series and grouped in amplifier stages with each stage having at least one amplifier. In between each amplfier stage is a filter which restricts the bandwidth of signals to frequencies in a desired signal range. When an amplifier stage includes more than one amplifier, a local summer sums the outputs detected by detectors associated with each amplifier in a particular stage. When an amplifier stage includes only a single amplifier associated detector, the local sum signal for the stage is simply the detector output. No local summer is required. Because of the time delay introduced by each interposed filter, each local sum is input to a corresponding compensating device which compensates for the associated time delay. Each compensating device stores its corresponding local sum until the local sum from the final stage is ready to be output. When all of the local summer outputs have been time-aligned or brought in phase, the local sums are connected from their corresponding compensating devices to a central summer stage. The output of the central summer represents the instantaneous output of the logarithmically amplified input signal.
Inventors
- 👤 Paul W. Dent
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 06:47
CPC Classifications
H; H03; H03D; H03D1/00; H03G; H03G7/00; H03G7/001; H04; H04B; H04B1/00; H04B1/06; H04B1/16
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
127 words
An apparatus for logarithmically amplifying an input signal comprising: a plurality of amplifiers connected in series and grouped in at least two amplifier stages said input signal being received in a first amplifier of a first amplifier stage and each amplifier stage generating an output signal; frequency bandwidth limiting filter means disposed between successive amplifier stages with each filter means delaying signal outputs between successive stages by a time delay period; compensating means associated with and responsive to at least some of said amplifier stages for compensating output signals from corresponding amplifier stages for a time delay period corresponding to an associated filter means to align said output signals in time; and a central summing means for summing the compensated output signals received from said compensating means.
Claim 2
Independent Claim
127 words
An apparatus for logarithmically amplifying an input signal comprising: a plurality of amplifiers connected in series and grouped in at least two amplifier stages said input signal being received in a first amplifier of a first amplifier stage and each amplifier stage generating an output signal; frequency bandwidth limiting filter means disposed between successive amplifier stages with each filter means delaying signal outputs between successive stages by a time delay period; compensating means associated with and responsive to at least some of said amplifier stages for compensating output signals from corresponding amplifier stages for a time delay period corresponding to an associated filter means to align said output signals in time; and a central summing means for summing the compensated output signals received from said compensating means.
Claim 3
Dependent Claim
28 words
The apparatus as defined in claim 1, wherein said amplifier stages include single amplifier stages having a single amplifier and multiple amplifier stages having at least two amplifiers.
Claim 4
Dependent Claim
43 words
The apparatus as defined in claim 2, further comprising a plurality of rectifiers associated with said plurality of amplifiers, each rectifier detecting an output signal from a corresponding amplifier and generating a detected output signal to which said associated compensating means is responsive.
Claim 5
Dependent Claim
91 words
The apparatus as defined in claim 3, further comprising: a plurality of local summing devices associated with said multiple amplifier stages for summing detected output signals of each amplifier in an associated multiple amplifier stage to generate a local sum equivalent to a total detected stage output, wherein the total detected stage output of one of said single amplifier stages is equivalent to the detected stage output, and wherein an associated compensating means receives the total detected stage output of an amplifier stage to compensate for an associated time delay period.
Claim 6
Dependent Claim
52 words
The apparatus as defined in claim 4, wherein said associated compensating means comprises: a plurality of memories connected by way of a corresponding plurality of first switches to the total detected stage output of an associated amplifier stage, a plurality of second switches correspondingly connecting said memories to said central summing means.
Claim 7
Dependent Claim
42 words
The apparatus as defined in claim 5, wherein each one of said compensating means receives control signals from a digital logic circuit programmed to selectively activate and deactivate individual ones of said first and second switches based on said associated time delay.
Claim 8
Dependent Claim
38 words
The apparatus as defined in claim 6, wherein said digital logic circuit compensates for said associated time delays in two adjustment modes: a first mode for achieving coarse time delay adjustment and a second mode achieving fine adjustment.
Claim 9
Dependent Claim
37 words
The apparatus as defined in claim 7, wherein during said first mode, said digital logic circuit cyclically activates and deactivates individual ones of said first and second switches to generate a predetermined number of time delay periods.
Claim 10
Dependent Claim
52 words
The apparatus as defined in claim 7, wherein during said second mode, said digital logic circuit varies the relative phase between the activation of individual ones of said first switches and the activation of individual ones of said second switches to generate time delays greater or less than one time delay period.
Claim 11
Dependent Claim
31 words
The apparatus as defined in claim 5, wherein each of said memories is a capacitor such that the charge stored in said capacitor is proportional to the value to be stored.
Claim 12
Dependent Claim
19 words
The apparatus as defined in claim 10, wherein said capacitor memories convert local sum current signals to voltage signals.
Claim 13
Dependent Claim
48 words
The apparatus as defined in claim 11, wherein said central summing means includes a means for connecting selected capacitor memories from each compensating means thereby permitting charge sharing between said selected capacitors to generate an output proportional to the sum of the outputs from each local summing device.
Claim 14
Dependent Claim
67 words
The apparatus as defined in claim 4, wherein said associated compensating means comprises: a plurality of delay elements such that each delay element is related to the number of time delay periods the total detected stage output from a given amplifier stage must be delayed in order to align said total detected stage output in time with the total detected stage output of a final amplifier stage.
Claim 15
Dependent Claim
55 words
The apparatus as defined in claim 4, wherein for n amplifier stages, the total detected output of the i-th amplifier stage is delayed by the sum of (n-i) time periods T(i)+T(i+1)+. . . +T(n-1) j where T(i) is the filter delay between the i-th and the (i+1)-th amplifier stages and i=1 . . . n.
Claim 16
Dependent Claim
46 words
The apparatus as defined in claim 14, wherein each compensating means includes n memories connected by way of a first set of n switches to the output of an associated local summing device and by a second set of n switches to said central summing means.
Claim 17
Dependent Claim
38 words
The apparatus as defined in claim 15, further comprising a digital logic circuit for generating signals for selectively opening and closing each of said first set of n switches and each of said second set of n switches.
Claim 18
Dependent Claim
51 words
The apparatus as defined in claim 15, wherein each of said first switches may be closed to store an associated local sum in an associated memory and each of said second switches may be closed to send the associated local sum stored in the associated memory to said central summing means.
Claim 19
Dependent Claim
35 words
The apparatus as defined in claim 15, wherein each of said plurality of compensating means includes a third set of n switches connected to said n memories for selectively resetting individual ones of said memories.
Claim 20
Dependent Claim
24 words
The apparatus as defined in claim 18, further comprising a digital logic circuit for selectively opening and closing said third set of n switches.
References Cited (Backward Citations)
US3423682A
Cited
US3403347A
Cited
US3435353A
Cited
US3605027A
Cited
US3668535A
Cited
US3745474A
Cited
US3745374A
Cited
US4090150A
Cited
US4442549A
Cited
US4551688A
Cited
US4574251A
Cited
US4716316A
Cited
US4780681A
Cited
US4797586A
Cited
US4972512A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-12-02 | 1995-06-03 | 1995-12-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-12-02 | 1999-06-03 | 1999-12-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-12-02 | 2003-06-03 | 2003-12-03 | $7700.00 | Window Closed / Lapsed |