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US4090150A Expired / Lapsed US ⏱️ 0.0 years remaining

High dynamic phase-accurate alternating voltage amplifier operating as a logarithmic amplifier for maintaining amplitude information

Assignee: Siemens AG
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Filing: 1977-01-24
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Granted: 1978-05-16
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Expires: 1997-01-24
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Abstract

Abstract An amplifier circuit for the unadulterated transmission of phase information of a supplied ac voltage signal over a large dynamic range includes a series connection of a series of similar amplifier stages each of which is followed by a symmetrical limiter. The amplifier operates as a logarithmic amplifier for maintaining the amplitude information of the supplied ac signal. Each of the amplifier stages comprise an emitter-base transistor amplifier circuit having negative feedback and an output circuit which contains a resonant circuit which is strongly damped by an attenuating resistor and whose capacitance is formed by a trimmer capacitor connected in parallel to a pair of diodes. The diodes are connected in anti-parallel relation to one another and represent the limiter. The capacitance is adjustable for purpose of impedance adjustment and is set in such a manner that the resultant resonant circuit impedance is capacitive.

Inventors

  • 👤 Erwin Vachenauer

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 11:47
CPC Classifications
H; H03; H03G; H03G7/00; H03G7/001; G; G01; G01S; G01S7/00; G01S7/02; G01S7/28; H03G11/00; H03G11/002

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 111 words
A multi-stage limiter amplifier for amplifying an ac voltage of a specific frequency which may have been subjected to large level fluctuations, comprising: a plurality of serially-connected amplifier stages each including a feedback amplifier and a pair of limiter diodes connected to the output of said feedback amplifier, said diodes connected in opposite polarity and in parallel and having a symmetrical limiting effect, each of said amplifier stages including a transistor amplifier circuit comprising an output circuit including a parallel resonant circuit, a damping impedance strongly damping said parallel resonant circuit, said parallel resonant circuit including a trimmer capacitor connected in parallel to said limiter diodes for rendering said impedance capacitive.
Claim 2
Dependent Claim 111 words
A multi-stage limiter amplifier for amplifying an ac voltage of a specific frequency which may have been subjected to large level fluctuations, comprising: a plurality of serially-connected amplifier stages each including a feedback amplifier and a pair of limiter diodes connected to the output of said feedback amplifier, said diodes connected in opposite polarity and in parallel and having a symmetrical limiting effect, each of said amplifier stages including a transistor amplifier circuit comprising an output circuit including a parallel resonant circuit, a damping impedance strongly damping said parallel resonant circuit, said parallel resonant circuit including a trimmer capacitor connected in parallel to said limiter diodes for rendering said impedance capacitive.
Claim 3
Dependent Claim 49 words
The amplifier of claim 1, comprising: a plurality of rectifiers connected to the limiter diodes at the outputs of said amplifier stages; and adding means connected to said rectifiers for providing an output signal which is at least approximately the logarithmic of the signals received by said amplifier stages.
Claim 4
Dependent Claim 25 words
The amplifier of claim 2, comprising: a plurality of buffer amplifiers, each of said buffer amplifiers connected between said amplifier stages and said adding means.
Claim 5
Dependent Claim 39 words
The amplifier of claim 2, wherein: the amplification of each of said amplifier stages is small compared to the total required amplification thereby requiring a larger number of said amplifier stages for more accurate conformity to a logarithmic characteristic.

References Cited (Backward Citations)

US3319176A Cited
US3403347A Cited
US3605027A Cited
US3717820A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1981-05-15 1981-11-14 1982-05-16 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1985-05-15 1985-11-14 1986-05-16 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1989-05-15 1989-11-14 1990-05-16 $7700.00 Window Closed / Lapsed

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