Meter drive circuit

Claim 3

In an FM receiver which includes an IF limiter system having a plurality of cascaded, transistor differential stages of substantially equal gain, each stage having a differential stage common node associated therewith, a method for producing an output signal that varies as the logarithm of an input signal supplied to the IF limiter system, comprising the steps of: producing D.C. voltage changes at the common nodes of particular ones of said stages of the IF limiter system as said particular stages go into limiting; detecting said D.C. voltage changes to provide corresponding current changes; and accumulating said current changes to provide the output signal.

Claim 4

In an FM receiver which includes an IF limiter system having a plurality of cascaded, transistor differential stages of substantially equal gain, each stage having a differential stage common node associated therewith, a method for producing an output signal that varies as the logarithm of an input signal supplied to the IF limiter system, comprising the steps of: producing D.C. voltage changes at the common nodes of particular ones of said stages of the IF limiter system as said particular stages go into limiting; detecting said D.C. voltage changes to provide corresponding current changes; and accumulating said current changes to provide the output signal.

Claim 5

In an IF limiter system including a plurality of cascaded, transistor differential stages of substantially equal gain, each stage having a differential stage common node, a method for producing an output signal as each stage of the IF limiter goes into limiting which varies linearly with the logarithm of an input signal supplied to the IF limiter, comprising the steps of: producing a D.C. voltage change at the common mode of each stage as each stage goes into limiting; detecting said D.C. voltage changes to provide corresponding current changes; and summing said current changes to produce the output signal.

Claim 6

In an IF limiter system including a plurality of cascaded, transistor differential stages of substantially equal gain, each stage having a differential stage common node, a method for producing an output signal as each stage of the IF limiter goes into limiting which varies linearly with the logarithm of an input signal supplied to the IF limiter, comprising the steps of: producing a D.C. voltage change at the common mode of each stage as each stage goes into limiting; detecting said D.C. voltage changes to provide corresponding current changes; and summing said current changes to produce the output signal.

Claim 7

A circuit including a plurality of differential amplifier stages connected in cascade, each of the amplifier stages having substantially the same gain and having a differential stage common node associated therewith, the circuit being responsive to an applied input signal for supplying an output signal the magnitude of which varies linearly with the logarithm of the input signal, comprising: circuit means for detecting a DC voltage change at the common nodes of particular ones of the stages as particular stages go into limiting to produce a plurality of current changes; summing means for accumulating said plurality of current changes; and output circuit means receiving said accumulated current changes for supplying the output signal.

Claim 8

A circuit including a plurality of differential amplifier stages connected in cascade, each of the amplifier stages having substantially the same gain and having a differential stage common node associated therewith, the circuit being responsive to an applied input signal for supplying an output signal the magnitude of which varies linearly with the logarithm of the input signal, comprising: circuit means for detecting a DC voltage change at the common nodes of particular ones of the stages as particular stages go into limiting to produce a plurality of current changes; summing means for accumulating said plurality of current changes; and output circuit means receiving said accumulated current changes for supplying the output signal.

Claim 9

The circuit of claim 4 wherein said circuit means includes a plurality of individual transistors each having first, second and control electrodes, said first electrode of each transistor being coupled to a first terminal at which is supplied a bias potential, said second electrode of each transistor being coupled to said summing means, said control electrode of each transistor being coupled to a respective common node of a particular one of the differential amplifier stages.

Claim 10

The circuit of claim 5 wherein said output circuit means is a current turn-around circuit having an input and an output, said input being coupled to said summing means, said output being coupled to an output of the circuit.

Claim 11

In a FM receiver including an IF limiter having a plurality of substantially equal gain transistor differential amplifier stages connected in cascade to receive an IF input signal, a circuit for producing a signal the magnitude of which varies linearly with the logarithm of the IF input signal, comprising: circuit means responsive to particular ones of the differential amplifier stages going into limiting for detecting a DC voltage change produced at a common node of each of said particular differential amplifier stages to produce a plurality of current changes; means for summing said current changes; and current turn-around means receiving said summed currents for supplying the signal at an output.

Claim 12

In a FM receiver including an IF limiter having a plurality of substantially equal gain transistor differential amplifier stages connected in cascade to receive an IF input signal, a circuit for producing a signal the magnitude of which varies linearly with the logarithm of the IF input signal, comprising: circuit means responsive to particular ones of the differential amplifier stages going into limiting for detecting a DC voltage change produced at a common node of each of said particular differential amplifier stages to produce a plurality of current changes; means for summing said current changes; and current turn-around means receiving said summed currents for supplying the signal at an output.

Claim 13

The circuit of claim 7 wherein said circuit means includes a plurality of individual transistors each having first, second and control electrodes, said first electrode of each transistor being coupled to a first terminal at which is supplied a bias potential, said second electrode of each transistor being coupled to said summing means, said control electrode of each transistor being coupled to a respective common node of a particular one of the differential amplifier stages.

Claim 14

An IF limiter system including a plurality of differential transistor stages of substantially equal gain connected in cascade forming an IF limiter, the IF limiter receiving an input signal for supplying a first output signal that is symmetrically clipped, the improvement comprising a circuit responsive to particular ones of the stages going into a limiting mode for supplying a second output signal the magnitude of which varies linearly with the logarithm of the input signal, said circuit comprising: circuit means responsive to the particular differential amplifier stages for detecting a DC voltage change produced at a common node of each particular differential amplifier stage to produce a plurality of current changes; means for summing said current changes; and current turn-around means for supplying the second output signal in response to said summed current changes.

Claim 15

An IF limiter system including a plurality of differential transistor stages of substantially equal gain connected in cascade forming an IF limiter, the IF limiter receiving an input signal for supplying a first output signal that is symmetrically clipped, the improvement comprising a circuit responsive to particular ones of the stages going into a limiting mode for supplying a second output signal the magnitude of which varies linearly with the logarithm of the input signal, said circuit comprising: circuit means responsive to the particular differential amplifier stages for detecting a DC voltage change produced at a common node of each particular differential amplifier stage to produce a plurality of current changes; means for summing said current changes; and current turn-around means for supplying the second output signal in response to said summed current changes.

Claim 16

The circuit of claim 9 wherein said circuit means includes a plurality of individual transistors each having first, second and control electrodes, said first electrode of each transistor being coupled to a first terminal at which is supplied a bias potential, said second electrode of each transistor being coupled to said summing means, said control electrode of each transistor being coupled to a respective common node of a particular one of the differential amplifier stages.