Combined tuning and signal strength indicator circuit with signal strength indication derived from each if amplifying stage

Claim 2

In a system for receiving radio signals, a combined tuning and signal strength indicator arrangement comprising: a plurality of cascaded signal amplifying stages; separate rectifying means coupled to each of said amplifying stages for providing a succession of outputs representative of increasing magnitude of said received signal; common biasing means for maintaining each of said rectifying means at a conduction threshold in the absence of received signals; combining means coupled to each of said rectifying means for combining said outputs; and indicating means coupled to said combining means for providing a display indicative of received signal strength.

Claim 3

A tuning and signal strength indicator arrangement according to claim 1 wherein: each said rectifying means comprises a transistor having emitter, base and collector electrodes, each said collector electrode being coupled to a terminal adapted for connection to a source of operating potential; and said biasing means is coupled to the base electrodes of said transistors for biasing said transistors to the threshold of conduction; and said emitter electrodes being coupled to said combining means for providing said outputs.

Claim 4

A tuning and signal strength indicator arrangement according to claim 2 wherein said rectifying means further comprises capacitive filtering means coupled to said emitter electrodes.

Claim 5

A tuning and signal strength indicator arrangement according to claim 2 further including a capacitor coupled between The emitter electrode of at least one of said transistors and said reference terminal.

Claim 6

A tuning and signal strength indicator arrangement according to claim 1 wherein said common biasing means includes stabilizing means for maintaining said rectifying means at said conduction threshold in the presence of operating potential supply variations.

Claim 7

A tuning and signal strength indicator arrangement according to claim 5 wherein said stabilizing means provides compensation for temperature variations of components in said circuit.

Claim 8

A tuning and signal strength indicator circuit according to claim 6 wherein said combining means comprises a current duplicator circuit, including a diode having an anode and a cathode, and an output transistor having emitter, base, and collector electrodes, the emitter electrode of said output transistor being coupled to said anode, the base electrode of said output transistor being coupled to the cathode of said diode and the collector electrode of said third transistor being coupled to said indicating means.

Claim 9

A tuning and signal strength indicator arrangement according to claim 7 wherein at least one of said stages includes a frequency responsive network tuned to a frequency related to received signals; and said indicating means is responsive to variations in the output of said combining means for indicating tuning.

Claim 10

A combined tuning and signal strength indicator circuit comprising: a plurality of signal translating amplifiers having input and output terminals, coupled in cascade, at least one of said signal translating amplifiers including a tuned network; means providing a source of input signals coupled to the input terminal of the first of said signal translating amplifiers; rectifying means coupled to the output terminal of each of said signal translating amplifiers for providing a plurality of direct current signals representative of received signal amplitude; common biasing means for maintaining each of said rectifying means at a conductive threshold in the absence of received signals; summing means coupled to each said rectifying means for summing said direct current signals; and indicating means coupled to said summing means for providing a display indicative of tuning and received signal strength.

Claim 11

A combined tuning and signal strength indicator circuit comprising: a plurality of signal translating amplifiers having input and output terminals, coupled in cascade, at least one of said signal translating amplifiers including a tuned network; means providing a source of input signals coupled to the input terminal of the first of said signal translating amplifiers; rectifying means coupled to the output terminal of each of said signal translating amplifiers for providing a plurality of direct current signals representative of received signal amplitude; common biasing means for maintaining each of said rectifying means at a conductive threshold in the absence of received signals; summing means coupled to each said rectifying means for summing said direct current signals; and indicating means coupled to said summing means for providing a display indicative of tuning and received signal strength.

Claim 12

A combined tuning and signal strength indicator circuit according to claim 9 wherein: each said rectifying means comprises a first transistor, having emitter, base, and collector electrodes, each said collector electrode being coupled to a terminal adapted for connection to a source of operating potential; and said biasing means is coupled to the base electrodes of said transistors for biasing said transistors to the threshold of conduction; and each said rectifying means further comprises a second transistor, having base, emitter, and collector electrodes, each of said last-named collector electrodes being coupled through said summing means to said operating potential terminal, each said last-named base electrode being coupled to the emitter electrode of a corresponding one of said first transistors, and the emitter electrode of each said transistor being coupled to a reference terminal.

Claim 13

A combined tuning and signal strength indicator circuit according to claim 10 wherein said summing means comprises a current duplicator circuit, including a diode having an anode and a cathode, said anode being coupled to said operating potential terminal, a third transistor having emitter, base, and collector electrodes, the emitter electrode of said third transistor being coupled to said operating potential terminal, the base electrode of said third transistor being coupled to the cathode of said diode and the collector electrode of said second transistors, the collector electrode of said third transistor being coupled to said indicating means.