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Silicon integrated circuit with passive devices over high resistivity silicon substrate portion, and active devices formed in lower resistivity silicon layer over the substrate

Assignee: Northrop Grumman Corp
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Filing: 1995-03-07
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Granted: 1996-09-24
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Expires: 2015-03-07
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Abstract

Abstract A silicon microwave monolothic integrated circuit device and method of fabricating having a high resistivity silicon substrate with a masking layer of low temperature silicon oxide, silicon nitride and polysilicon sublayers on a first area, and an epitaxial layer over the surface of the silicon substrate in a second area. The active devices are formed over the second area and the passive devices are formed over the first area.

Inventors

  • 👤 James R. Cricchi
  • 👤 Paul A. Potyraj
  • 👤 Mike L. Salib

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 08:33
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/40; H10D84/401

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 145 words
A silicon microwave monolithic integrated circuit device comprising: a high resistivity silicon substrate of a first conductivity type; a masking layer formed over a first area of said substrate comprising a plurality of sub-layers of silicon dioxide atop said first area of said substrate: silicon nitride atop said silicon dioxide sub-layer: and oxidized polysilicon atop said sub-layer of silicon nitride; a well region formed in said substrate and doped with second conductivity type dopant forming a second area of said substrate: a silicon epitaxial layer formed over said second area of said substrate, said silicon epitaxial layer having a second resistivity lower than said high resistivity; a microwave bipolar junction transistor (BJT) formed in said silicon epitaxial layer and a portion of said second area of said substrate; and a passive element formed over said masking layer and said first area of said silicon substrate.
Claim 2
Dependent Claim 145 words
A silicon microwave monolithic integrated circuit device comprising: a high resistivity silicon substrate of a first conductivity type; a masking layer formed over a first area of said substrate comprising a plurality of sub-layers of silicon dioxide atop said first area of said substrate: silicon nitride atop said silicon dioxide sub-layer: and oxidized polysilicon atop said sub-layer of silicon nitride; a well region formed in said substrate and doped with second conductivity type dopant forming a second area of said substrate: a silicon epitaxial layer formed over said second area of said substrate, said silicon epitaxial layer having a second resistivity lower than said high resistivity; a microwave bipolar junction transistor (BJT) formed in said silicon epitaxial layer and a portion of said second area of said substrate; and a passive element formed over said masking layer and said first area of said silicon substrate.
Claim 3
Dependent Claim 20 words
The device of claim 1 wherein the high resistivity of the silicon substrate is at least one thousand ohms centimeter.
Claim 4
Dependent Claim 25 words
The device of claim 1 wherein the low resistivity of the silicon epitaxial layer is in the range of approximately 0.8 to 10 ohms centimeter.
Claim 5
Dependent Claim 17 words
The device of claim 1 wherein the masking layer has a thickness of approximately 3 thousand angstroms.
Claim 6
Dependent Claim 19 words
The device of claim 1 further comprising an oxide layer overlaying both the masking layer and the epitaxial layer.

References Cited (Backward Citations)

US5449953A Cited
US5268315A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1999-09-24 2000-03-25 2000-09-24 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2003-09-24 2004-03-25 2004-09-24 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2007-09-24 2008-03-25 2008-09-24 $7700.00 Window Closed / Lapsed

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