Arbitration device for arbitrating access requests from first and second processors having different first and second clocks

Claim 1

An arbitration device for shared RAM, the arbitration device arbitrating between first and second access requests from first and second processors having respectively different first and second clocks, said arbitration device comprising: a synchronizer which synchronizes the first access request to the second clock so as to obtain first and second clock-synchronized access requests; a delay which delays one of the clock-synchronized requests by a fractional part of the second clock so as to obtain first and second time-offset access requests; a hold off circuit which outputs first and second access grant signals, exactly one of the first and second access grant signals being activated in correspondence to which of the first and second time-offset access requests is first to arrive at said hold off circuit, wherein the first access grant signal is activated in a case where the first time-offset access request arrives before the second time-offset access request and the second time-offset access request is held off until processing of the first time-offset access request is complete, and wherein the second access grant signal is activated in a case where the second time-offset access request arrives before the first time-offset access request and the first time-offset access request is held off until processing of the second time-offset access request is complete; a re-synchronizer which re-synchronizes the first access grant signal to the first clock; and a shared RAM interface, responsive to the first and second access grant signals, so as to give the first processor access to shared RAM in a case where the first access grant signal is output by said hold off circuit, and so as to give the second processor access to the shared RAM in a case where the second access grant signal is output by said hold off circuit.