Patent US5828340A successfully refreshed from Google Patents.
Patent US5557769A successfully refreshed from Google Patents.
US5557769A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Mechanism and protocol for maintaining cache coherency within an integrated processor
Assignee: Advanced Micro Devices Inc
•
Filing: 1994-06-17
•
Granted: 1996-09-17
•
Expires: 2014-06-17
Abstract
Abstract An integrated processor includes CPU core, cache memory, and cache controller coupled to a local bus via a local bus interface. The integrated processor further includes memory controller for coupling system memory to the local bus, and a bus interface unit for coupling external peripheral devices to the local bus. The cache controller includes an address tag and state logic circuit which keeps track of a physical address in system memory which corresponds to each entry within cache memory. Address tag and state logic circuit contains state information that indicates whether each cache line is valid and/or dirty. The cache controller includes a snoop control circuit which monitors the local bus to determine whether a memory cycle has been executed by an alternate bus master. During such a memory cycle of an alternate bus master, a comparator circuit determines whether a cache hit has occurred. If a cache read hit occurs with respect to a dirty cache line, the cache controller asserts an inhibit signal which causes the memory controller to ignore the cycle. The read request is instead serviced by the cache controller by providing the requested data from the cache memory to local bus 112. If a cache write operation occurs, data is written into the system memory via system memory controller, and the data is concurrently latched into the corresponding line of the cache memory. The status of cache line may further be updated to clean if the data transfer encompassed a complete cache line.
Inventors
- 👤 Joseph A. Bailey
- 👤 Steve L. Belt
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 16:41
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0806; G06F12/0815; G06F12/0831; G06F12/0835
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
300 words
A computer system comprising: a system bus; a system memory; an alternate bus master coupled to said system bus wherein said bus master is configured to execute a memory cycle on said system bus; and an integrated processor formed on a single semiconductor chip including: a bus interface unit configured to couple said system bus to a local bus; a cache memory operatively coupled to said local bus; a processing unit coupled to said cache memory; a system memory controller operatively coupled to said local bus and to said system memory and configured to control the storage and retrieval of data within said system memory; a cache controller operatively coupled to said cache memory and to said local bus configured to control the storage and retrieval of data within said cache memory, wherein said cache controller includes: a tag logic circuit configured to store a plurality of line addresses indicative of a plurality of lines of data stored within said cache memory and configured to store at least one dirty bit associated with each line; a comparator circuit coupled to said tag logic circuit configured to determine whether a cache hit has occurred during a designated memory cycle; and a snoop control circuit coupled to said comparator circuit, wherein said snoop control circuit is configured to inhibit said memory controller during a read cycle which is associated with dirty cached data, wherein said snoop control circuit is configured to cause said dirty cached data to be driven on said local bus in response to said memory cycle; and wherein said snoop control circuit is further configured to latch data to be stored within a corresponding memory location of said cache memory during a write operation of said alternate bus master, and to concurrently latch said data within said memory controller.
Claim 2
Dependent Claim
300 words
A computer system comprising: a system bus; a system memory; an alternate bus master coupled to said system bus wherein said bus master is configured to execute a memory cycle on said system bus; and an integrated processor formed on a single semiconductor chip including: a bus interface unit configured to couple said system bus to a local bus; a cache memory operatively coupled to said local bus; a processing unit coupled to said cache memory; a system memory controller operatively coupled to said local bus and to said system memory and configured to control the storage and retrieval of data within said system memory; a cache controller operatively coupled to said cache memory and to said local bus configured to control the storage and retrieval of data within said cache memory, wherein said cache controller includes: a tag logic circuit configured to store a plurality of line addresses indicative of a plurality of lines of data stored within said cache memory and configured to store at least one dirty bit associated with each line; a comparator circuit coupled to said tag logic circuit configured to determine whether a cache hit has occurred during a designated memory cycle; and a snoop control circuit coupled to said comparator circuit, wherein said snoop control circuit is configured to inhibit said memory controller during a read cycle which is associated with dirty cached data, wherein said snoop control circuit is configured to cause said dirty cached data to be driven on said local bus in response to said memory cycle; and wherein said snoop control circuit is further configured to latch data to be stored within a corresponding memory location of said cache memory during a write operation of said alternate bus master, and to concurrently latch said data within said memory controller.
Claim 3
Dependent Claim
19 words
The computer system as recited in claim 1 wherein said read cycle is initiated by said alternate bus master.
Claim 4
Dependent Claim
17 words
The computer system as recited in claim 1 wherein said alternate bus master is a bus bridge.
Claim 5
Dependent Claim
29 words
The computer system as recited in claim 1 wherein said cache line is marked clean by said tag logic circuit if said write operation involves an entire cache line.
Claim 6
Dependent Claim
276 words
An integrated processor formed on a single semiconductor chip comprising: a CPU core; a bus operatively coupled to said CPU core and configured to transfer data signals; a cache memory operatively coupled to said bus; a system memory controller operatively coupled to said bus and configured to control the storage and retrieval of data within a system memory; an alternative bus master device coupled to said bus, wherein said alternate bus master device is configured to execute a memory cycle on said bus; and a cache controller operatively coupled to said cache memory and to said bus configured to control the storage and retrieval of data within said cache memory, wherein said cache controller includes: a tag logic circuit configured to store a plurality of line addresses indicative of a plurality of lines of data stored within said cache memory and configured to store at least one dirty bit associated with each line; a comparator circuit coupled to said tag logic circuit configured to determine whether a cache hit has occurred during a designated memory cycle; and a snoop control circuit coupled to said comparator circuit, wherein said snoop control circuit is configured to inhibit said memory controller during a read cycle which is associated with dirty cached data, and said snoop control circuit is configured to cause said dirty cached data to be driven on said local bus in response to said memory cycle; said snoop control circuit being further configured to latch data to be stored within a corresponding memory location of said cache memory during a write operation of said alternate bus master, and to concurrently latch said data within said memory controller.
Claim 7
Dependent Claim
276 words
An integrated processor formed on a single semiconductor chip comprising: a CPU core; a bus operatively coupled to said CPU core and configured to transfer data signals; a cache memory operatively coupled to said bus; a system memory controller operatively coupled to said bus and configured to control the storage and retrieval of data within a system memory; an alternative bus master device coupled to said bus, wherein said alternate bus master device is configured to execute a memory cycle on said bus; and a cache controller operatively coupled to said cache memory and to said bus configured to control the storage and retrieval of data within said cache memory, wherein said cache controller includes: a tag logic circuit configured to store a plurality of line addresses indicative of a plurality of lines of data stored within said cache memory and configured to store at least one dirty bit associated with each line; a comparator circuit coupled to said tag logic circuit configured to determine whether a cache hit has occurred during a designated memory cycle; and a snoop control circuit coupled to said comparator circuit, wherein said snoop control circuit is configured to inhibit said memory controller during a read cycle which is associated with dirty cached data, and said snoop control circuit is configured to cause said dirty cached data to be driven on said local bus in response to said memory cycle; said snoop control circuit being further configured to latch data to be stored within a corresponding memory location of said cache memory during a write operation of said alternate bus master, and to concurrently latch said data within said memory controller.
Claim 8
Dependent Claim
19 words
The integrated processor as recited in claim 5 wherein said read cycle is initiated by said alternate bus master.
Claim 9
Dependent Claim
17 words
The integrated processor as recited in claim 5 wherein said alternate bus master is a bus bridge.
Claim 10
Dependent Claim
29 words
The integrated processor as recited in claim 5 wherein said cache line is marked clean by said tag logic circuit if said write operation involves an entire cache line.
Claim 11
Dependent Claim
158 words
A cache control method for an integrated processor formed on a single semiconductor chip comprising the steps of: storing a plurality of line addresses indicative of a plurality of lines of data within a cache memory; storing a plurality of dirty bits associated with each line address; initiating a memory read cycle to transfer data from a system memory to an alternate bus master; detecting said memory cycle within a cache controller; determining whether a corresponding line resides within said cache memory; determining whether said corresponding line is dirty; inhibiting said system memory from providing data of a requested address to said alternate bus master if said corresponding line resides within said cache memory and if said line is dirty; providing said data corresponding to said requested address from said cache memory; and latching data concurrently within said memory controller and a corresponding memory location of said cache memory during a write operation of said alternate bus master.
Claim 12
Dependent Claim
158 words
A cache control method for an integrated processor formed on a single semiconductor chip comprising the steps of: storing a plurality of line addresses indicative of a plurality of lines of data within a cache memory; storing a plurality of dirty bits associated with each line address; initiating a memory read cycle to transfer data from a system memory to an alternate bus master; detecting said memory cycle within a cache controller; determining whether a corresponding line resides within said cache memory; determining whether said corresponding line is dirty; inhibiting said system memory from providing data of a requested address to said alternate bus master if said corresponding line resides within said cache memory and if said line is dirty; providing said data corresponding to said requested address from said cache memory; and latching data concurrently within said memory controller and a corresponding memory location of said cache memory during a write operation of said alternate bus master.
References Cited (Backward Citations)
WO1990000285A1
Cited
US5119485A
Cited
EP0428149A2
Cited
US5355467A
Cited
US5353423A
Cited
US5325504A
Cited
US5426765A
Cited
EP0567355A2
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-17 | 2000-03-18 | 2000-09-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-17 | 2004-03-18 | 2004-09-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-17 | 2008-03-18 | 2008-09-17 | $7700.00 | Window Closed / Lapsed |