Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
193 words
A system comprising a processor (48) having a processor address bus and a processor data bus, said processor being capable of performing locked write instruction sequences, a cache memory (42) having a plurality of locations for storing data, said cache memory (42) having a cache data bus coupled to said processor data bus, a system bus (56) including system address lines and system data lines, a main memory having a plurality of locations for storing data, said main memory (60) being coupled to said system address lines and system data lines, and a peripheral device coupled to said system address lines and system data lines, said system characterized by comprising: control means (44) coupled to said processor address bus, processor data bus, cache memory (42), system address lines and system data lines for permitting said peripheral device to gain control over said system bus, said control means stopping operation of said processor before the onset of a locked write instruction if said peripheral has control of said system bus, and wherein when said processor commences a locked instruction sequence, said control means prevents said peripheral device from gaining control over said system bus.
Claim 2
Independent Claim
193 words
A system comprising a processor (48) having a processor address bus and a processor data bus, said processor being capable of performing locked write instruction sequences, a cache memory (42) having a plurality of locations for storing data, said cache memory (42) having a cache data bus coupled to said processor data bus, a system bus (56) including system address lines and system data lines, a main memory having a plurality of locations for storing data, said main memory (60) being coupled to said system address lines and system data lines, and a peripheral device coupled to said system address lines and system data lines, said system characterized by comprising: control means (44) coupled to said processor address bus, processor data bus, cache memory (42), system address lines and system data lines for permitting said peripheral device to gain control over said system bus, said control means stopping operation of said processor before the onset of a locked write instruction if said peripheral has control of said system bus, and wherein when said processor commences a locked instruction sequence, said control means prevents said peripheral device from gaining control over said system bus.
Claim 3
Dependent Claim
107 words
System of claim 1, further characterized in that said microprocessor commences all locked instruction sequences with a locked read instruction, said microprocessor communicating a locked instruction signal to said control means (44) during execution of locked instructions, said processor (48) having a ready input line for receiving a ready signal, said ready signal indicating the presence of valid data on said processor data bus, wherein during the commencement of a lock read instruction by said processor while said peripheral device controls said system bus, said control means asserts said ready input line false to stop said processor until said peripheral device relinquishes control over said system bus.
Claim 4
Dependent Claim
104 words
System of claim 2, further characterized in that said peripheral device includes an EHOLD signal line coupled to said control means (44) for communicating a request signal to said control means, said control means including an EHLDA signal line coupled to said peripheral device for permitting said control means to communicate an EHLDA signal to said peripheral device when said processor is not performing locked instructions, the receipt of said EHLDA signal by said peripheral device enabling said peripheral device to control said system bus, wherein said control means will not cause said EHLDA signal to go true when said processor performs locked instructions.