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US5555527A
Expired / Lapsed
US
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Semiconductor memory, moving-picture storing memory, moving-picture storing apparatus, moving-picture displaying apparatus, static-picture storing memory, and electronic notebook
Assignee: Panasonic Holdings Corp
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Filing: 1994-12-14
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Granted: 1996-09-10
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Expires: 2014-12-14
Abstract
Abstract A memory array divided into a plurality of sub-memory-arrays is disposed on a chip so that, if a specified sub-memory-array is selected by a sub-memory-array selecting circuit, a normal read/write operation is performed with respect to the sub-memory-array based on an address indicated by a group of external address signals. At the same time, a clock generator for self-refresh mounted on a chip generates a word-line basic clock for self-refresh and a word-line basic clock for refresh, thereby selecting the word lines in the sub-memory-arrays which have not been selected. Prior to a predetermined time at which the sub-memory-array subjected to a refresh operation is subsequently selected, a refresh halt signal is outputted so as to forcibly halt the refresh operation, thereby preventing insufficient recharging of a memory cell. Each of the plurality of sub-memory-arrays stores, of sequential sets of image data, data on one frame or one field.
Inventors
- 👤 Hisakazu Kotani
- 👤 Hironori Akamatsu
- 👤 Tsutomu Fujita
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 20:54
CPC Classifications
G; G06; G06F; G06F15/00; G09; G09G; G09G5/00; G09G5/36; G09G5/39; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/401; G11C11/406; G09G2360/00; G09G2360/12; G09G2360/123; G09G5/001
Claims Analysis
Total Claims: 20
Claim 1
Independent Claim
263 words
A semiconductor memory to which data can be sequentially inputted/outputted in synchronization with an external clock, comprising: a plurality of memory arrays disposed on a chip; a memory-array selecting circuit for selecting, in accordance with a group of addresses inputted from the outside, at least one memory array out of said plurality of memory arrays; refresh-signal generating means for generating a refresh address and a word-line basic clock for refresh; and address-selecting circuits which are equal in number to said memory arrays so as to correspond to said respective memory arrays, wherein each of said address-selecting circuits is constituted so that it selects, when the corresponding memory array is selected by said memory-array selecting circuit, a word line in said selected memory array in accordance with the group of addresses inputted from the outside and with a word-line basic clock, while it selects, when the corresponding memory array is not selected by said memory-array selecting circuit, word lines in said memory arrays which have not been selected in accordance with the refresh address and the word-line basic clock for refresh generated by said refresh-signal generating means, said semiconductor memory further comprising: a pre-switching-time predicting circuit for predicting a time point immediately before a predetermined time at which each of the memory arrays is switched from the unselected state to the selected state by said memory-array selecting circuit; and a refresh inhibit circuit for inhibiting said refresh-signal generating means from generating the word-line basic clock for refresh at the time point immediately before the predetermined time which was predicted by said pre-switching-time predicting circuit.
Claim 2
Dependent Claim
263 words
A semiconductor memory to which data can be sequentially inputted/outputted in synchronization with an external clock, comprising: a plurality of memory arrays disposed on a chip; a memory-array selecting circuit for selecting, in accordance with a group of addresses inputted from the outside, at least one memory array out of said plurality of memory arrays; refresh-signal generating means for generating a refresh address and a word-line basic clock for refresh; and address-selecting circuits which are equal in number to said memory arrays so as to correspond to said respective memory arrays, wherein each of said address-selecting circuits is constituted so that it selects, when the corresponding memory array is selected by said memory-array selecting circuit, a word line in said selected memory array in accordance with the group of addresses inputted from the outside and with a word-line basic clock, while it selects, when the corresponding memory array is not selected by said memory-array selecting circuit, word lines in said memory arrays which have not been selected in accordance with the refresh address and the word-line basic clock for refresh generated by said refresh-signal generating means, said semiconductor memory further comprising: a pre-switching-time predicting circuit for predicting a time point immediately before a predetermined time at which each of the memory arrays is switched from the unselected state to the selected state by said memory-array selecting circuit; and a refresh inhibit circuit for inhibiting said refresh-signal generating means from generating the word-line basic clock for refresh at the time point immediately before the predetermined time which was predicted by said pre-switching-time predicting circuit.
Claim 3
Dependent Claim
67 words
A semiconductor memory according to claim 1, wherein the refresh-signal generating means consists of: a timer circuit for determining a refresh cycle; a clock generator for generating a clock for self-refresh and the word-line basic clock for refresh during the refresh cycle determined by said timer circuit; and a refresh counter for receiving the clock for self-refresh generated by said clock generator and generating the refresh address.
Claim 4
Dependent Claim
50 words
A semiconductor memory according to claim 2, wherein the single timer circuit and the single clock generator are provided in the refresh-signal generating means and the refresh counters, which are equal in number to the plurality of memory arrays, are provided so as to correspond to the respective memory arrays.
Claim 5
Dependent Claim
131 words
A semiconductor memory according to claim 1, wherein the pre-switching-time predicting circuit is composed of a counter using the word-line basic clock as a clock for increment and of a counted number detecting circuit for detecting the number counted by said counter and the refresh inhibit circuit is composed of a refresh halt control circuit for inhibiting the refresh-signal generating means from generating the word-line basic clock for refresh by outputting a refresh halt signal to the refresh-signal generating means during the period during which the counted number detected by said counted-number detecting circuit is within the range of a number smaller by a specified value than a predetermined counted number obtained at the time at which the memory array is switched to the selected state to said predetermined counted number.
Claim 6
Dependent Claim
26 words
A semiconductor memory according to claim 4, wherein the refresh halt control-circuit outputs the refresh halt signal to the clock generator of the refresh-signal generating means.
Claim 7
Dependent Claim
124 words
A semiconductor memory according to claim 1, further comprising: an access-completion detecting circuit for detecting the completion of access to data on one word line in the memory array selected by the memory-array selecting circuit; a normal-operation-halt control circuit for halting the selection of the memory array by said memory-array selecting circuit from the time at which said access-completion detecting circuit detected the completion of the access on, so that the address-selecting circuit selects a word line in said memory array in accordance with the refresh address of the refresh-signal generating means; and a cycle setting circuit for setting, when said normal-operation-halt control circuit halted the selection of the memory array, a shorter increment cycle for the refresh address of said refresh-signal generating means.
Claim 8
Dependent Claim
155 words
A semiconductor memory according to claim 6, wherein the access-completion detecting circuit is composed of a clock counter which is reset by a basic clock for column for fetching a column address and which is incremented by an external clock having a cycle time shorter than the cycle time of the clock for self-refresh from the refresh-signal generating means and of a counted number detecting circuit for detecting a coincidence of the number counted by said clock counter with the predetermined counted number obtained at the time at which the access to the data on the word line is completed and the cycle setting circuit is composed of a clock selecting circuit for outputting, when the normal-operation-halt control circuit halted the selection of the memory array, a clock of a frequency corresponding to the frequency of said external clock as the clock for increment, in place of the clock for self-refresh from the clock generator.
Claim 9
Dependent Claim
48 words
A semiconductor memory according to claim 7, wherein the clock counter is controlled so that it operates when the frequency of the external clock is equal to or lower than a predetermined value and halts the operation when the frequency of the external clock exceeds the predetermined value.
Claim 10
Dependent Claim
28 words
A semiconductor memory according to claim 7, wherein the clock selecting circuit outputs, as the clock for increment, the external clock as it is to the refresh counter.
Claim 11
Dependent Claim
53 words
A semiconductor memory according to claim 7, further comprising a frequency divider for dividing the frequency of the external clock, wherein the clock selecting circuit outputs, to the refresh counter, a clock of a frequency resulting from the frequency of the external clock divided by the frequency divider as the clock for increment.
Claim 12
Dependent Claim
142 words
A semiconductor memory according to claim 1, 4, 6, or 7, further comprising a delay circuit for generating a delayed word-line basic clock for refresh by delaying the word-line basic clock for refresh generated by the refresh-signal generating means by a predetermined period within the increment cycle for the refresh address generated by said refresh-signal generating means, wherein the word-line basic clock for refresh generated by said refresh-signal generating means and the delayed word-line basic clock for refresh generated by said delay circuit are inputted to the address-selecting circuits corresponding to the plurality of memory arrays which have not been selected by the memory-array selecting circuit and the operation of activating and inactivating the word lines for refreshing the plurality of memory arrays which have not been selected by said memory-array selecting circuit is performed at different times for different memory arrays.
Claim 13
Dependent Claim
71 words
A semiconductor memory according to claim 11, wherein the delay circuit generates the delayed word-line basic clocks for refresh provided with different delay times, said delayed word-line basic clocks for refresh being equal in number to the memory arrays which have not been selected by the memory-array selecting circuit and the plurality of memory arrays which have not been selected by said memory-array selecting circuit are sequentially refreshed at different times.
Claim 14
Dependent Claim
142 words
A semiconductor memory according to claim 12, wherein the delay circuit comprises: a ring oscillator for receiving the clock for self-refresh and generating, every time the clock for self-refresh is inputted, a clock having a cycle shorter than the cycle of said clock for self-refresh; and shift register circuits having multiple stages equal in number to the memory arrays which have not been selected by the memory-array selecting circuit, wherein the output from said ring oscillator is used as a clock for transfer in each stage of said shift register circuits, the word-line basic clock for refresh from the refresh-signal generating means is inputted to the first stage of said shift register circuits, and the outputs from the individual stages of said shift register circuits are used as the plurality of delayed word-line basic clocks for refresh provided with different delay times.
Claim 15
Dependent Claim
70 words
A semiconductor memory according to claim 13, further comprising a delay device for delaying the output from the ring oscillator, wherein the output from said delay device is used as another clock for transfer in each stage of the shift register circuits and each of the delayed word-line basic clocks for refresh is set by the output from said delay device and reset by the output from said ring oscillator.
Claim 16
Dependent Claim
103 words
A semiconductor memory according to claim 2, 4, 6, 7, 12, or 13, further comprising a selection detecting circuit for detecting the presence or absence of a memory array selected by the memory-array selecting circuit, wherein the timing period of the timer circuit is set to a predetermined period when said selection detecting circuit detected the state in which none of the memory arrays had been selected, while the timing period of the timer circuit is set to a period shorter than said predetermined period when said selection detecting circuit detected the state in which any of the memory arrays had been selected.
Claim 17
Dependent Claim
129 words
A semiconductor memory according to claim 15, wherein the selection detecting circuit is composed of an OR circuit for receiving a memory array select signal outputted from the memory-array selecting circuit and the timer circuit is composed of a first timer circuit for determining a first refresh cycle and of a second timer circuit for determining a second refresh cycle which is shorter than said first refresh cycle, said semiconductor memory further comprising a refresh-cycle selecting circuit for selecting, in accordance with the output from said OR circuit serving as a control signal, said first timer circuit when none of the memory arrays outputting signals at the Low level was selected or said second timer when any of the memory arrays outputting signals at the High level was selected.
Claim 18
Dependent Claim
130 words
A semiconductor memory comprising a plurality of memory arrays disposed on a chip, wherein a normal read/write operation is performed with respect to a selected memory array at the same time that a refresh operation is performed with respect to the memory arrays which have not been selected said semiconductor memory further comprising: a selection detecting circuit for detecting the presence or absence of said selected memory array; and a timer circuit for setting a refresh cycle to a predetermined period when said selection detecting circuit detected the state in which none of the memory arrays had been selected, while setting the refresh cycle to a period shorter than said predetermined period when said selection detecting circuit selected the state in which any of the memory arrays had been selected.
Claim 19
Dependent Claim
130 words
A semiconductor memory comprising a plurality of memory arrays disposed on a chip, wherein a normal read/write operation is performed with respect to a selected memory array at the same time that a refresh operation is performed with respect to the memory arrays which have not been selected said semiconductor memory further comprising: a selection detecting circuit for detecting the presence or absence of said selected memory array; and a timer circuit for setting a refresh cycle to a predetermined period when said selection detecting circuit detected the state in which none of the memory arrays had been selected, while setting the refresh cycle to a period shorter than said predetermined period when said selection detecting circuit selected the state in which any of the memory arrays had been selected.
Claim 20
Dependent Claim
53 words
A semiconductor memory according to claim 1, wherein each of the plurality of memory arrays disposed serves as a sub-memory-array for storing, of sequential sets of image data, data on one image, said semiconductor memory further comprising additional data input/output means For inputting and outputting data to and from each of said sub-memory-arrays.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-10 | 2000-03-11 | 2000-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-10 | 2004-03-11 | 2004-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-10 | 2008-03-11 | 2008-09-10 | $7700.00 | Window Closed / Lapsed |