Patent US5555392A successfully refreshed from Google Patents.
US5555392A
Expired / Lapsed
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Method and apparatus for a line based non-blocking data cache
Assignee: Intel Corp
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Filing: 1993-10-01
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Granted: 1996-09-10
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Expires: 2013-10-01
Abstract
Abstract A method and apparatus for providing a non-blocking cache that uses substantially less die area than a prior art non-blocking cache. In the present invention, pending count and ignore fill fields are added to each line of the cache. These fields are used in conjunction with a valid field (that indicates whether or not the line contains valid data) to keep track of the status of pending load operations that have resulted in cache misses. The pending field keeps a count of the number of outstanding load misses for the line. If a store occurs for an address of a line, the ignore fill field is set to indicate that any fills that are pending for the line are to be ignored because the pending fills will be supplying stale data to the line.
Inventors
- 👤 Robert B. Chaput
- 👤 Randy L. Steck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-08 15:57
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/0802; G06F12/0844; G06F12/0855; G06F12/0859
Claims Analysis
Total Claims: 12
Claim 1
Independent Claim
245 words
A non-blocking data cache that contains data for use by a processor, comprising: a data random access memory (RAM) that contains a plurality of lines of data; a tag RAM coupled to the data RAM that contains information relating to each line of the plurality of lines of data, information relating to a line of data in the data RAM comprising: an address tag; a pending count; an ignore indicator; a comparator coupled to the tag RAM that compares a tag address with the address tag, the tag address being part of a physical address from the processor, and generates a hit indication indicating that data identified by the tag address from the processor is contained in the data RAM when the address tag matches the tag address, and generates a miss indication otherwise; means responsive to the miss indication for causing the tag RAM to increment the pending count, wherein a non-zero pending count indicates that at least one fill to the line of data in the data RAM is pending, and for causing the tag RAM to decrement the pending count each time a fill to the line of data in the data RAM has been completed; and means responsive to the ignore indicator for ignoring a fill operation to the line of data in the data RAM when the pending count is not zero and data having a line address of the line of data in the data RAM has been stored.
Claim 2
Dependent Claim
245 words
A non-blocking data cache that contains data for use by a processor, comprising: a data random access memory (RAM) that contains a plurality of lines of data; a tag RAM coupled to the data RAM that contains information relating to each line of the plurality of lines of data, information relating to a line of data in the data RAM comprising: an address tag; a pending count; an ignore indicator; a comparator coupled to the tag RAM that compares a tag address with the address tag, the tag address being part of a physical address from the processor, and generates a hit indication indicating that data identified by the tag address from the processor is contained in the data RAM when the address tag matches the tag address, and generates a miss indication otherwise; means responsive to the miss indication for causing the tag RAM to increment the pending count, wherein a non-zero pending count indicates that at least one fill to the line of data in the data RAM is pending, and for causing the tag RAM to decrement the pending count each time a fill to the line of data in the data RAM has been completed; and means responsive to the ignore indicator for ignoring a fill operation to the line of data in the data RAM when the pending count is not zero and data having a line address of the line of data in the data RAM has been stored.
Claim 3
Dependent Claim
57 words
The non-blocking cache of claim 1, wherein the information relating to a line of data in the data RAM further comprises a valid indicator that indicates that the line of data in the data RAM is valid when a fill to the line of data in the data RAM is completed and the pending count is zero.
Claim 4
Independent Claim
189 words
A method of operation for a cache memory of a microprocessor system comprising the steps of: (A) receiving a first physical address from the microprocessor comprising at least a tag address and a line address; (B) comparing the tag address to an address tag of a tag random access memory (RAM) of the cache; (C) generating a hit indication in response to a match between the tag address and the address tag, otherwise generating a miss indication; (D) using the line address to identify a line of data in a data RAM of the cache to be accessed in response to the hit indication; (E) incrementing a pending count in the tag RAM in response to the miss indication; (F) decrementing the pending count in the tag RAM when a fill operation to the line of data has been completed; (G) receiving a next physical address; (H) repeating steps (A) through (F) irrespective of the pending count; and (I) setting an ignore fill indicator in the tag RAM when data having the line address has been stored for use by the microprocessor and the pending count is not zero.
Claim 5
Independent Claim
189 words
A method of operation for a cache memory of a microprocessor system comprising the steps of: (A) receiving a first physical address from the microprocessor comprising at least a tag address and a line address; (B) comparing the tag address to an address tag of a tag random access memory (RAM) of the cache; (C) generating a hit indication in response to a match between the tag address and the address tag, otherwise generating a miss indication; (D) using the line address to identify a line of data in a data RAM of the cache to be accessed in response to the hit indication; (E) incrementing a pending count in the tag RAM in response to the miss indication; (F) decrementing the pending count in the tag RAM when a fill operation to the line of data has been completed; (G) receiving a next physical address; (H) repeating steps (A) through (F) irrespective of the pending count; and (I) setting an ignore fill indicator in the tag RAM when data having the line address has been stored for use by the microprocessor and the pending count is not zero.
Claim 6
Dependent Claim
20 words
The method of claim 3, further comprising the step of (J) performing step (H) irrespective of the ignore fill indicator.
Claim 7
Dependent Claim
44 words
The method of claim 4, further comprising the steps of: (K) setting a valid indicator in the tag RAM when a fill to the line of data is completed and the pending count is zero; (L) performing step H irrespective of the valid indicator.
Claim 8
Dependent Claim
266 words
A computer system comprising: a processor; a main memory coupled to the processor, the main memory comprising a plurality of storage locations, each storage location having a physical address comprising at least a tag address and a line address identifying the line of data; a cache memory coupled to the processor and to the main memory, the cache comprising: a data random access memory (RAM) containing a plurality of lines of data; a tag RAM coupled to the data RAM, the tag RAM containing information relating to each line of the plurality of lines of data in the data RAM, information relating to a line of data in the data RAM comprising: an address tag; a pending count; an ignore fill indicator; a comparator coupled to the tag RAM that compares the tag address with the address tag, the comparator generating a hit indication indicating that data identified by the tag address is contained in the data RAM when the address tag matches the tag address, the comparator generating a miss indication otherwise; means responsive to the miss indication for causing the tag RAM to increment a pending count, wherein a non-zero pending count indicates that at least one fill to the line of data is pending, and for causing the tag RAM to decrement the pending count each time a fill to the line of data is completed; means responsive to the ignore indicator for ignoring a fill operation to the line of data when the pending count is not zero and data having a line address of the line of data has been stored.
Claim 9
Dependent Claim
266 words
A computer system comprising: a processor; a main memory coupled to the processor, the main memory comprising a plurality of storage locations, each storage location having a physical address comprising at least a tag address and a line address identifying the line of data; a cache memory coupled to the processor and to the main memory, the cache comprising: a data random access memory (RAM) containing a plurality of lines of data; a tag RAM coupled to the data RAM, the tag RAM containing information relating to each line of the plurality of lines of data in the data RAM, information relating to a line of data in the data RAM comprising: an address tag; a pending count; an ignore fill indicator; a comparator coupled to the tag RAM that compares the tag address with the address tag, the comparator generating a hit indication indicating that data identified by the tag address is contained in the data RAM when the address tag matches the tag address, the comparator generating a miss indication otherwise; means responsive to the miss indication for causing the tag RAM to increment a pending count, wherein a non-zero pending count indicates that at least one fill to the line of data is pending, and for causing the tag RAM to decrement the pending count each time a fill to the line of data is completed; means responsive to the ignore indicator for ignoring a fill operation to the line of data when the pending count is not zero and data having a line address of the line of data has been stored.
Claim 10
Dependent Claim
48 words
The computer system of claim 6, wherein the information relating to a line of data in the data RAM further comprises a valid indicator indicating that the line of data is valid when a fill to the line of data is completed and the pending count is zero.
Claim 11
Dependent Claim
258 words
A non-blocking data cache containing data for use by a processor, comprising: a data random access memory (RAM) containing a plurality of lines of data; a tag RAM coupled to the data RAM containing information relating to each line of the plurality of lines of data, information relating to a line of data comprising: an address tag; a valid indicator; a pending count; an ignore indicator; a comparator coupled to the tag RAM that compares a tag address with the address tags, the tag address being part of a physical address from the processor, the comparator generating a hit indication indicating that data identified by the tag address from the processor is available in the data RAM when the address tag matches the tag address the comparator generating a miss indication otherwise; means responsive to the miss indication for causing the tag RAM to increment the pending count, a non-zero pending count indicating that at least one fill to the line of data is pending, and for causing the tag RAM to decrement the pending count each time a fill to the line of data is completed; means responsive to the ignore indicator for ignoring a fill operation to the line of data when the pending count is not zero and data having a line address of the line of data has been stored for use by the processor; and wherein the valid indicator indicating that the line of data is valid when a fill to the line of data is completed and the pending count is zero.
Claim 12
Dependent Claim
258 words
A non-blocking data cache containing data for use by a processor, comprising: a data random access memory (RAM) containing a plurality of lines of data; a tag RAM coupled to the data RAM containing information relating to each line of the plurality of lines of data, information relating to a line of data comprising: an address tag; a valid indicator; a pending count; an ignore indicator; a comparator coupled to the tag RAM that compares a tag address with the address tags, the tag address being part of a physical address from the processor, the comparator generating a hit indication indicating that data identified by the tag address from the processor is available in the data RAM when the address tag matches the tag address the comparator generating a miss indication otherwise; means responsive to the miss indication for causing the tag RAM to increment the pending count, a non-zero pending count indicating that at least one fill to the line of data is pending, and for causing the tag RAM to decrement the pending count each time a fill to the line of data is completed; means responsive to the ignore indicator for ignoring a fill operation to the line of data when the pending count is not zero and data having a line address of the line of data has been stored for use by the processor; and wherein the valid indicator indicating that the line of data is valid when a fill to the line of data is completed and the pending count is zero.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-10 | 2000-03-11 | 2000-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-10 | 2004-03-11 | 2004-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-10 | 2008-03-11 | 2008-09-10 | $7700.00 | Window Closed / Lapsed |