Method and apparatus for constructing unique input/output sequence (UIO) sets utilizing transition distinctness measurements

Claim 1

A method for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said method comprising the steps of: (a) identifying all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, and all Identified State Transition (TR) Set Members are State Transitions (TR); (b) identifying all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) selecting one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) identifying each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) providing control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) providing control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) providing said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) associating the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) repeating steps (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; and (j) utilizing at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS).

Claim 2

A method for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said method comprising the steps of: (a) identifying all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, and all Identified State Transition (TR) Set Members are State Transitions (TR); (b) identifying all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) selecting one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) identifying each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) providing control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) providing control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) providing said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) associating the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) repeating steps (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; and (j) utilizing at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS).

Claim 12

A method for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said method comprising the steps of: (a) identifying all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, all Identified State Transition (TR) Set Members are State Transitions (TR), and all State Transitions (TR) are members of the Identified State Transition (TR) Set; (b) identifying all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) selecting one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) identifying each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) providing control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) providing control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) providing said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) associating the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) repeating steps (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; (j) utilizing at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS) (k) identifying all members of a Second Identified State Transition (TR) Subset, wherein: each of the members of the Second Identified State Transition (TR) Subset is a Second Identified State Transition (TR) Subset Member, all Second Identified State Transition (TR) Subset Members are Identified State Transition (TR) Set Members, said Second Identified State Transition (TR) Subset contains at least one Second Identified State Transition (TR) Subset Member; and (l) providing control signals to the computer processor to compare the I/O Sequence Distinctness Measurement (DM) associated with at least one Second Identified State Transition (TR) Subset Member to the I/O Sequence Distinctness Measurement (DM) associated with one other Second Identified State Transition (TR) Subset Member in order to determine which of the Second Identified State Transition (TR) Subset Members has a comparatively lower associated I/O Sequence Distinctness Measurement (DM) and which of the Second Identified State Transition (TR) Subset Members has a comparatively higher associated I/O Sequence Distinctness Measurement (DM); wherein: utilizing the I/O Sequence Distinctness Measurement (DM) includes searching the Second Identified State Transition (TR) Subset Member with the comparatively lower associated I/O Sequence Distinctness Measurement (DM) before searching the Second Identified State Transition (TR) Subset Member with the comparatively higher I/O Sequence Distinctness Measurement (DM) when identifying an Identified Unique I/O Sequence (UIO) Set.

Claim 13

A method for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said method comprising the steps of: (a) identifying all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, all Identified State Transition (TR) Set Members are State Transitions (TR), and all State Transitions (TR) are members of the Identified State Transition (TR) Set; (b) identifying all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) selecting one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) identifying each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) providing control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) providing control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) providing said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) associating the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) repeating steps (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; (j) utilizing at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS) (k) identifying all members of a Second Identified State Transition (TR) Subset, wherein: each of the members of the Second Identified State Transition (TR) Subset is a Second Identified State Transition (TR) Subset Member, all Second Identified State Transition (TR) Subset Members are Identified State Transition (TR) Set Members, said Second Identified State Transition (TR) Subset contains at least one Second Identified State Transition (TR) Subset Member; and (l) providing control signals to the computer processor to compare the I/O Sequence Distinctness Measurement (DM) associated with at least one Second Identified State Transition (TR) Subset Member to the I/O Sequence Distinctness Measurement (DM) associated with one other Second Identified State Transition (TR) Subset Member in order to determine which of the Second Identified State Transition (TR) Subset Members has a comparatively lower associated I/O Sequence Distinctness Measurement (DM) and which of the Second Identified State Transition (TR) Subset Members has a comparatively higher associated I/O Sequence Distinctness Measurement (DM); wherein: utilizing the I/O Sequence Distinctness Measurement (DM) includes searching the Second Identified State Transition (TR) Subset Member with the comparatively lower associated I/O Sequence Distinctness Measurement (DM) before searching the Second Identified State Transition (TR) Subset Member with the comparatively higher I/O Sequence Distinctness Measurement (DM) when identifying an Identified Unique I/O Sequence (UIO) Set.

Claim 14

An apparatus for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said apparatus comprising: (a) means for identifying all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, and all Identified State Transition (TR) Set Members are State Transitions (TR); (b) means for identifying all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) means for selecting one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) means for identifying each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) means for providing control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) means for providing control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) means for providing said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) means for associating the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) means for repeating elements (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; and (j) means for utilizing at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS).

Claim 15

An apparatus for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said apparatus comprising: (a) means for identifying all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, and all Identified State Transition (TR) Set Members are State Transitions (TR); (b) means for identifying all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) means for selecting one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) means for identifying each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) means for providing control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) means for providing control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) means for providing said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) means for associating the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) means for repeating elements (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; and (j) means for utilizing at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS).

Claim 16

An apparatus for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said apparatus comprising: (a) a computer processor programmed to identify all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, and all Identified State Transition (TR) Set Members are State Transitions (TR); (b) the computer processor programmed to identify all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) the computer processor programmed to select one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) the computer processor programmed to identify each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) the computer processor programmed to provide control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) the computer processor programmed to provide control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) the computer processor programmed to provide said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) the computer processor programmed to associate the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) the computer processor programmed to repeat elements (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; and (j) the computer processor programmed to utilize at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS).

Claim 17

An apparatus for measuring an I/O Sequence Distinctness Measurement (DM) for an I/O Sequence associated with model state transitions in a Finite State Machine (FSM) model, the I/O Sequence being used in constructing a Verification Test Sequence (VTS) to test a Machine Under Test (MUT) for conformance against the FSM model, wherein: said FSM model has a plurality of Model States (ST) and a plurality of State Transitions (TR), each of the plurality of State Transitions (TR) is located between a First Model State (ST) and a Second Model State (ST) in the FSM model, each of the plurality of State Transitions (TR) has a corresponding I/O Sequence, and each I/O Sequence includes an Input Stimulus and an Output Response, said apparatus comprising: (a) a computer processor programmed to identify all members of an Identified State Transition (TR) Set, wherein: each member of the Identified State Transition (TR) Set is an Identified State Transition (TR) Set Member, and all Identified State Transition (TR) Set Members are State Transitions (TR); (b) the computer processor programmed to identify all members of an Identified I/O Sequence Set, wherein: each member of the Identified I/O Sequence Set is an Identified I/O Sequence Set Member, each member of the Identified I/O Sequence Set is different from each other member of the Identified I/O Sequence Set, and the I/O Sequence corresponding to each Identified TR Set Member is equal to one member of the Identified I/O Sequence Set; (c) the computer processor programmed to select one member of the Identified I/O Sequence Set as a Selected I/O Sequence; (d) the computer processor programmed to identify each member of a First Identified State Transition (TR) Subset, wherein: each member of the First Identified State Transition (TR) Subset is a First Identified State Transition (TR) Subset Member, said First identified State Transition (TR) Subset contains at least one First Identified TR Subset Member, each First Identified State Transition (TR) Subset Member is one of the Identified TR Set Members, the I/O Sequence corresponding to each First Identified State Transition (TR) Subset Member is equal to the Selected I/O Sequence, and all Identified State Transition (TR) Set Members with corresponding I/O Sequences equal to the Selected I/O Sequence are First Identified State Transition (TR) Subset Members; (e) the computer processor programmed to provide control signals to direct a computer processor to calculate an I/O Sequence Distinctness Count by counting the First Identified State Transition (TR) Subset Members; (f) the computer processor programmed to provide control signals to direct the computer processor to calculate the I/O Sequence Distinctness Measurement (DM) by applying a transformation to the I/O Sequence Distinctness Count; (g) the computer processor programmed to provide said I/O Sequence Distinctness Measurement (DM) for storage in a memory; (h) the computer processor programmed to associate the I/O Sequence Distinctness Measurement (DM) with every one of the First Identified State Transition (TR) Subset Members; (i) the computer processor programmed to repeat elements (c)-(h) until each Identified I/O Sequence Set Member has been selected one time; and (j) the computer processor programmed to utilize at least one said I/O Sequence Distinctness Measurement (DM) in the generation of the Verification Test Sequence (VTS).