US5554568A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Polysilicon trench and buried polysilicon wall device structures
Assignee: United Microelectronics Corp
•
Filing: 1994-12-27
•
Granted: 1996-09-10
•
Expires: 2014-12-27
Abstract
Abstract This invention describes a device structure and a method of forming the device structure using trenches with sidewalls formed in the substrate of an integrated circuit. A highly doped polysilicon layer is formed on the walls of the trench or the trench is filled with highly doped polysilicon to form the source and drain of a field effect transistor in an integrated circuit. The invention provides reduced source and drain resistance. The capacitances between the gate and source and the gate and drain are reduced as well.
Inventors
- 👤 Jemmy Wen
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 04:58
CPC Classifications
H; H10; H10D; H10D62/00; H10D62/10; H10D62/13; H10D62/149; H10D62/151; H10D62/01; H10D62/021; H10D62/113; H10D62/115; H10D62/116; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/013; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S257/00; Y10S257/903
Claims Analysis
Total Claims: 15
Claim 1
Independent Claim
169 words
A method of forming a trench device, comprising the steps of: providing a semiconductor substrate; forming a barrier dielectric layer on the surface of said semiconductor substrate; forming a layer of photoresist with openings for source and drain regions in said layer of photoresist on said barrier dielectric layer; forming vertical trenches in said semiconductor substrate through said openings in said layer of photoresist wherein each of said vertical trenches has a top, a bottom, and sidewalls; removing remaining said layer of photoresist; filling said vertical trenches with doped polysilicon wherein said doped polysilicon contacts said sidewalls of said vertical trenches; annealing said doped polysilicon and said sidewalls of said vertical trenches; removing said barrier dielectric layer on said surface of said semiconductor substrate; forming a gate dielectric layer on said surface of said semiconductor substrate wherein said gate dielectric layer covers said tops of said vertical trenches; forming a gate electrode layer on said gate dielectric layer; and forming a gate electrode pattern in said gate dielectric layer.
Claim 2
Independent Claim
169 words
A method of forming a trench device, comprising the steps of: providing a semiconductor substrate; forming a barrier dielectric layer on the surface of said semiconductor substrate; forming a layer of photoresist with openings for source and drain regions in said layer of photoresist on said barrier dielectric layer; forming vertical trenches in said semiconductor substrate through said openings in said layer of photoresist wherein each of said vertical trenches has a top, a bottom, and sidewalls; removing remaining said layer of photoresist; filling said vertical trenches with doped polysilicon wherein said doped polysilicon contacts said sidewalls of said vertical trenches; annealing said doped polysilicon and said sidewalls of said vertical trenches; removing said barrier dielectric layer on said surface of said semiconductor substrate; forming a gate dielectric layer on said surface of said semiconductor substrate wherein said gate dielectric layer covers said tops of said vertical trenches; forming a gate electrode layer on said gate dielectric layer; and forming a gate electrode pattern in said gate dielectric layer.
Claim 3
Dependent Claim
28 words
The method of claim 1 wherein said each of said vertical trenches is between about 0.5 and 1.0 microns wide and between about 0.5 and 5.0 microns deep.
Claim 4
Dependent Claim
15 words
The method of claim 1 wherein said gate dielectric layer is formed of silicon dioxide.
Claim 5
Dependent Claim
14 words
The method of claim 1 wherein said gate electrode layer is formed of polysilicon.
Claim 6
Dependent Claim
21 words
The method of claim 1 wherein the minimum distance between said sidewalls of adjacent said vertical trenches is about 0.1 microns.
Claim 7
Dependent Claim
13 words
The method of claim 1 wherein said barrier dielectric layer is an oxide.
Claim 8
Independent Claim
185 words
A method of forming a trench device, comprising the steps of: providing a semiconductor substrate; forming a barrier dielectric layer on the surface of said semiconductor substrate; forming a layer of photoresist with openings for source and drain regions in said layer of photoresist on said barrier dielectric layer; forming vertical trenches in said semiconductor substrate through said openings in said layer of photoresist wherein each of said vertical trenches has a top, a bottom, and sidewalls; removing remaining said layer of photoresist; forming a layer of doped polysilicon having a thickness of between about 500 and 2000 Angstroms on said sidewalls of said vertical trenches; filling the remainder of said vertical trenches with a filler dielectric; annealing said doped polysilicon and said sidewalls of said vertical trenches; removing said barrier dielectric layer on said surface of said semiconductor substrate; forming a gate dielectric layer on said surface of said semiconductor substrate wherein said gate dielectric layer covers said tops of said vertical trenches; forming a gate electrode layer on said gate dielectric layer; and forming a gate electrode pattern in said gate dielectric layer.
Claim 9
Independent Claim
185 words
A method of forming a trench device, comprising the steps of: providing a semiconductor substrate; forming a barrier dielectric layer on the surface of said semiconductor substrate; forming a layer of photoresist with openings for source and drain regions in said layer of photoresist on said barrier dielectric layer; forming vertical trenches in said semiconductor substrate through said openings in said layer of photoresist wherein each of said vertical trenches has a top, a bottom, and sidewalls; removing remaining said layer of photoresist; forming a layer of doped polysilicon having a thickness of between about 500 and 2000 Angstroms on said sidewalls of said vertical trenches; filling the remainder of said vertical trenches with a filler dielectric; annealing said doped polysilicon and said sidewalls of said vertical trenches; removing said barrier dielectric layer on said surface of said semiconductor substrate; forming a gate dielectric layer on said surface of said semiconductor substrate wherein said gate dielectric layer covers said tops of said vertical trenches; forming a gate electrode layer on said gate dielectric layer; and forming a gate electrode pattern in said gate dielectric layer.
Claim 10
Dependent Claim
12 words
The method of claim 7 wherein said filler dielectric is silicon dioxide.
Claim 11
Dependent Claim
28 words
The method of claim 7 wherein said each of said vertical trenches is between about 0.5 and 1.0 microns wide and between about 0.5 and 5.0 microns deep.
Claim 12
Dependent Claim
15 words
The method of claim 7 wherein said gate dielectric layer is formed of silicon dioxide.
Claim 13
Dependent Claim
14 words
The method of claim 7 wherein said gate electrode layer is formed of polysilicon.
Claim 14
Dependent Claim
21 words
The method of claim 7 wherein the minimum distance between said sidewalls of adjacent said vertical trenches is about 0.1 microns.
Claim 15
Dependent Claim
13 words
The method of claim 7 wherein said barrier dielectric layer is an oxide.
References Cited (Backward Citations)
US4520552A
Cited
US4835584A
Cited
US4963502A
Cited
US5111257A
Cited
US5293512A
Cited
US5204280A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1999-09-10 | 2000-03-11 | 2000-09-10 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2003-09-10 | 2004-03-11 | 2004-09-10 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2007-09-10 | 2008-03-11 | 2008-09-10 | $7700.00 | Window Closed / Lapsed |