US5554549A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Salicide process for FETs
Assignee: Taiwan Semiconductor Manufacturing Co TSMC Ltd
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Filing: 1995-07-03
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Granted: 1996-09-10
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Expires: 2015-07-03
Abstract
Abstract An LDD type of FET, based on the salicide process, is described. It is not subject to the possibility of short circuits occurring between the source and/or the drain region and the main substrate, by way of the lightly doped layer. In this structure, the lightly doped layers that form the upper portions of the source and drain regions extend inwards towards the gate region, thereby satisfying the design requirements of low area and high resistivity at the interface, but not outwards towards the poly/silicide conductors that make connection to the source and drain areas. A process for manufacturing this structure is described. An important difference between said process and the prior art is that the oxide spacers on the outside walls (away from the gate region) of the source/drain trenches are removed prior to the formation of the heavily doped portions of the source/drain, not after it.
Inventors
- 👤 Jenn-Ming Huang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-03 12:59
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/0223; H10D30/0227; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/0698
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
272 words
A process for manufacturing a field effect transistor and connections thereto, comprising: (a) providing a structure that comprises a body of P type silicon, including field isolating regions comprised of thick layers of silicon oxide, the surface of said silicon body being covered by a thin layer of silicon oxide in the regions between said field isolating regions; (b) depositing a layer of polycrystalline silicon over said structure; (c) patterning and then etching said thin layer of silicon oxide and said layer of polycrystalline silicon down to the level of the silicon body so as to form trenches on either side of a gate region that comprises the areas of the thin layer of silicon oxide and polycrystalline silicon that have not been removed; (d) then subjecting the structure to a first ion implantation of N type dopant material, to a dosage level such that the implanted silicon becomes lightly N type; (e) depositing silicon oxide on the side walls of said trenches and etching to form oxide spacers; (f) selectively removing the oxide spacers that are located on the side walls away from said gate region; (g) after step (f) subjecting the structure to a second ion implantation of N type dopant material to a dosage level such that the implanted silicon becomes strongly N type; (h) coating the structure with a layer of a refractory metal; (i) heating the structure until said refractory metal has been converted to a refractory metal silicide wherever it is in contact with silicon; and (j) etching the structure with an etchant that removes said refractory metal and does not remove said refractory metal silicide.
Claim 2
Dependent Claim
272 words
A process for manufacturing a field effect transistor and connections thereto, comprising: (a) providing a structure that comprises a body of P type silicon, including field isolating regions comprised of thick layers of silicon oxide, the surface of said silicon body being covered by a thin layer of silicon oxide in the regions between said field isolating regions; (b) depositing a layer of polycrystalline silicon over said structure; (c) patterning and then etching said thin layer of silicon oxide and said layer of polycrystalline silicon down to the level of the silicon body so as to form trenches on either side of a gate region that comprises the areas of the thin layer of silicon oxide and polycrystalline silicon that have not been removed; (d) then subjecting the structure to a first ion implantation of N type dopant material, to a dosage level such that the implanted silicon becomes lightly N type; (e) depositing silicon oxide on the side walls of said trenches and etching to form oxide spacers; (f) selectively removing the oxide spacers that are located on the side walls away from said gate region; (g) after step (f) subjecting the structure to a second ion implantation of N type dopant material to a dosage level such that the implanted silicon becomes strongly N type; (h) coating the structure with a layer of a refractory metal; (i) heating the structure until said refractory metal has been converted to a refractory metal silicide wherever it is in contact with silicon; and (j) etching the structure with an etchant that removes said refractory metal and does not remove said refractory metal silicide.
Claim 3
Dependent Claim
24 words
The process of claim 1 wherein the thickness of said thin layer of silicon oxide is between about 50 and about 500 Angstrom units.
Claim 4
Dependent Claim
23 words
The process of claim 1 wherein the thickness of said layer of polycrystalline silicon is between about 1,000 and about 5,000 Angstrom units.
Claim 5
Dependent Claim
39 words
The process of claim 1 wherein the voltage used to accelerate the ions in step (d) is between about 25 and about 80 kV, resulting in a penetration depth that is between about 800 and about 4,000 Angstrom units.
Claim 6
Dependent Claim
24 words
The process of claim 1 wherein the ion dosage achieved in step (d) is between about 10 13 and about 10 14 atoms/square centimeter.
Claim 7
Dependent Claim
39 words
The process of claim 1 wherein the voltage used to accelerate the ions in step (g) is between about 25 and about 80 kV, resulting in a penetration depth that is between about 800 and about 3,000 Angstrom units.
Claim 8
Dependent Claim
24 words
The process of claim 1 wherein the ion dosage used in step (g) is between about 10 15 and about 5×10 15 atoms/square centimeter.
Claim 9
Dependent Claim
20 words
The process of claim 1 wherein said refractory metal is taken from the group consisting of titanium, tungsten, and cobalt.
Claim 10
Dependent Claim
22 words
The process of claim 1 wherein the thickness of said refractory metal layer is between about 100 and about 1,000 Angstrom units.
Claim 11
Dependent Claim
35 words
The process of claim 1 wherein step (i) further comprises heating in an atmosphere of nitrogen at a temperature between about 500° and about 1,000 ° C. for from about 0.5 to about 1.5 minutes.
Claim 12
Dependent Claim
38 words
The process of claim 1 wherein step (j) further comprises immersion in an aqueous mixture of ammonia and hydrogen peroxide for between about 15 and about 45 minutes at a temperature between about 10° and about 30° C.
Claim 13
Dependent Claim
272 words
A process for forming a field effect transistor and connections thereto, comprising: (a) providing a structure that comprises a body of N type silicon, including field isolating regions comprised of thick layers of silicon oxide, the surface of said silicon body being covered by a thin layer of silicon oxide in the regions between said field isolating regions; (b) depositing a layer of polycrystalline silicon over said structure; (c) patterning and then etching said thin layer of silicon oxide and said layer of polycrystalline silicon down to the level of the silicon body so as to form trenches on either side of a gate region that comprises the areas of the thin layer of silicon oxide and polycrystalline silicon that have not been removed; (d) then subjecting the structure to a first ion implantation of P type dopant material, to a dosage level such that the implanted silicon becomes lightly P type; (e) depositing silicon oxide on the side walls of said trenches and etching to form oxide spacers; (f) selectively removing the oxide spacers that are located on the side walls away from said gate region; (g) after step (f) subjecting the structure to a second ion implantation of P type dopant material, to a dosage level such that the implanted silicon becomes strongly P type; (h) coating the structure with a layer of a refractory metal; (i) heating the structure until said refractory metal has been converted to a refractory metal silicide wherever it is in contact with silicon; and (j) etching the structure with an etchant that removes said refractory metal and does not remove said refractory metal silicide.
Claim 14
Dependent Claim
272 words
A process for forming a field effect transistor and connections thereto, comprising: (a) providing a structure that comprises a body of N type silicon, including field isolating regions comprised of thick layers of silicon oxide, the surface of said silicon body being covered by a thin layer of silicon oxide in the regions between said field isolating regions; (b) depositing a layer of polycrystalline silicon over said structure; (c) patterning and then etching said thin layer of silicon oxide and said layer of polycrystalline silicon down to the level of the silicon body so as to form trenches on either side of a gate region that comprises the areas of the thin layer of silicon oxide and polycrystalline silicon that have not been removed; (d) then subjecting the structure to a first ion implantation of P type dopant material, to a dosage level such that the implanted silicon becomes lightly P type; (e) depositing silicon oxide on the side walls of said trenches and etching to form oxide spacers; (f) selectively removing the oxide spacers that are located on the side walls away from said gate region; (g) after step (f) subjecting the structure to a second ion implantation of P type dopant material, to a dosage level such that the implanted silicon becomes strongly P type; (h) coating the structure with a layer of a refractory metal; (i) heating the structure until said refractory metal has been converted to a refractory metal silicide wherever it is in contact with silicon; and (j) etching the structure with an etchant that removes said refractory metal and does not remove said refractory metal silicide.
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