← Back to Patent Explorer
US5346860A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for fabricating an interconnect structure in an integrated circuit

Assignee: STMicroelectronics lnc USA
•
Filing: 1993-07-06
•
Granted: 1994-09-13
•
Expires: 2013-07-06
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A method for fabricating an interconnect structure in an integrated circuit. A first conductive layer is formed over an underlying region in the integrated circuit. The underlying region may be, for example, a semiconductor substrate or a gate electrode. A buffer layer is then formed over the first conductive layer, followed by the formation of an insulating layer over the buffer layer. The insulating layer and the buffer layer are patterned to define a form for the interconnect structure. A second conductive layer is then formed over the integrated circuit, and portions of the first conductive layer, the second conductive layer, and the buffer layer are silicided to form the interconnect structure.

Inventors

  • 👤 Che-Chia Wei

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-30 22:25
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/064; H10W20/066; H10W20/0698

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 94 words
A method for fabricating an interconnect structure in an integrated circuit, comprising the steps of: forming a first conductive layer over an underlying region in the integrated circuit; forming a buffer layer over the first conductive layer; forming an insulating layer over the buffer layer; patterning the insulating layer and the buffer layer to define a form for the interconnect structure; forming a second conductive layer over the integrated circuit; and annealing to form silicide from portions of the first and second conductive layers and the buffer layer, wherein the interconnect structure is formed.
Claim 2
Independent Claim 94 words
A method for fabricating an interconnect structure in an integrated circuit, comprising the steps of: forming a first conductive layer over an underlying region in the integrated circuit; forming a buffer layer over the first conductive layer; forming an insulating layer over the buffer layer; patterning the insulating layer and the buffer layer to define a form for the interconnect structure; forming a second conductive layer over the integrated circuit; and annealing to form silicide from portions of the first and second conductive layers and the buffer layer, wherein the interconnect structure is formed.
Claim 3
Dependent Claim 20 words
The method of claim 1, further comprising the steps of removing unsilicided portions of the first and second conductive layers.
Claim 4
Dependent Claim 29 words
The method of claim 1, wherein said step of forming a first conductive layer comprises depositing a thin layer of titanium over the underlying region in the integrated circuit.
Claim 5
Dependent Claim 13 words
The method of claim 3, wherein the underlying region comprises a semiconductor substrate.
Claim 6
Dependent Claim 12 words
The method of claim 3, wherein said underlying region comprises gate electrodes.
Claim 7
Dependent Claim 25 words
The method of claim 1, wherein said step of forming a buffer layer comprises depositing a layer of amorphous silicon over the first conductive layer.
Claim 8
Dependent Claim 23 words
The method of claim 1, wherein said step of forming an insulating layer comprises depositing a layer of oxide over the buffer layer.
Claim 9
Dependent Claim 24 words
The method of claim 1, wherein said step of forming a second conductive layer comprises depositing a layer of titanium over the integrated circuit.
Claim 10
Dependent Claim 32 words
The method of claim 1, wherein said step of siliciding portions of the first and second conductive layers comprises siliciding portions of the first and second conductive layers in a nitrogen ambient.

References Cited (Backward Citations)

US5121186A Cited
US4751198A Cited
US4822749A Cited
US4977098A Cited
JPH02199838A Cited
JPH0536632A Cited
US5173450A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1997-09-12 1998-03-14 1998-09-13 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2001-09-12 2002-03-14 2002-09-13 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2005-09-12 2006-03-14 2006-09-13 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag