Process for fabricating bipolar junction transistor having reduced parasitic capacitance

Abstract

Abstract A process for fabricating a BJT device on a semiconductor substrate is disclosed. The substrate serves as the collector. The process comprises the steps of, first, forming a shielding layer over the designated location over the surface of the substrate for defining the active region. The process further utilizes the shielding layer as the shielding mask for implanting impurities of into the substrate for forming an doped region. Then, a first field oxide layer is formed over the doped region and then removed. Sidewall spacers for the shielding layer are then formed. The process then utilizes the shielding layer and the sidewall spacers as the shielding mask for implanting impurities into portions of the doped region, forming a heavily-doped region, and the remaining portion of the doped region defines the base region. A second field oxide layer is then formed over the heavily-doped region. The sidewall spacers are then removed to form trenches in the places of the sidewall spacers. The process then forms emitter electrodes in the trenches, and then implants impurities into the base region via the emitter electrodes, thereby forming the emitter regions. The fabricated BJT has reduced inherent parasitic capacitance and improved switching speed characteristics.

Inventors

• 👤 Sheng-Hsing Yang

Bibliographic Details